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datasheet r01ds0097ej01 20 rev.1. 20 page 1 of 84 feb 20 , 201 3 rx610 group datasheet renesas 32 - bit mcu 1. overview 1.1 features the rx610 group is an mcu with the high - speed, high - performance rx cpu as its core. one basic instruction is executable in one cycle of the system clock. calculation functionality is further en hanced, with the inclusion of a single - precision floating - point calculation unit as well as a 32 - bit multiplier and divider. additionally, code efficiency is improved by instructions with lengths that are variable in byte units and by an enhanced range of addressing modes. timers, serial communication interfaces, i 2 c bus interfaces, an a/d converter, and a d/a converter are incorporated as peripheral functions which are essential to embedded devices. facilities for connecting external memory are also includ ed, enabling direct connection to memory and peripheral lsi circuits. the on - chip memory is flash memory capable of large - capacity, high - speed operation, and this significantly reduces the cost of configuring systems . 1.1.1 applications office automation equi pment and digital industrial equipment r01ds0097ej01 2 0 rev. 1.2 0 feb 2 0 , 201 3
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 2 of 84 feb 20 , 201 3 1.1.2 outline of specifications table 1.1 lists the specifications of the rx610 group in outline. table 1.1 outline of specifications classification module/function description cpu cpu ? maximum operating frequency: 100 mhz ? 32- bit rx cpu ? minimum ins truction execution time: one instruction in one state (in one system clock cycle) ? address space: 4 - gbyte linear address ? register set of the cpu general purpose: sixteen 32 - bit registers control: nine 32 - bit registers accumulator: one 64 - bit register ? basic instructions: 73 ? floating - point operation instructions: 8 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on - chip 32 - bit multiplier: 32 x 32 64 bits ? on - chip divider: 32 / 32 32 bits ? barrel shifter: 32 bits fpu ? single precision (32 - bit) floating point ? data types and floating - point exceptions conforming to the ieee754 standard memory flash ? flash capacity: 2 m bytes (max.) ? three types of on - board programming modes sci b oot mode, user program mode, and user boot mode ram ram capacity: 128 kbytes data flash data flash capacity: 32 kbytes mcu operating modes single - chip mode, on - chip rom enabled extended mode, and on - chip rom disabled extended mode clock clock generat ion circuit ? one main clock oscillation circuit ? includes a pll circuit and frequency divider, so the operating frequency is selectable ? system clock, peripheral module clock, and external bus clock are independently specifiable . the cpu , dmac, dtc, rom, and ram run in synchronization with the system clock ( iclk ): 8 to 100 mhz peripheral modules run in synchronization with the peripheral module clock ( pclk ): 8 to 50 mhz devices connected to the external bus run in synchronization with the external bus clock ( bclk): 8 to 25 mhz power down power - down function ? module stop function ? four power - down modes sleep mod e, all - module clock stop mode , software standby mode , and deep software standby mode
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 3 of 84 feb 20 , 201 3 classification module/function description interrupt interrupt control unit ? peripheral function interrupts : 116 ? external interrupts: 16 ( pins irq15 to irq0 ) ? non - maskable interrupt : 1 (the nmi pin ) ? eight priority orders specifiable external bus extension ? the external address space can be divided into eight areas ( cs0 to cs7), each of which is independently contr ollable . capacity of each area: 16 mbytes chip - select signals (cs0# to cs7#) can be output for each area. 8- bit or 16 - bit bus space can be specified for each area. the data arrangement is selectable as little endian or big endian for each area. (only for d ata) ? separate bus system ? wait control ? write buffer programming dma dma controller ? 4- channel dma transfer available ? activation sources: software trigger, external interrupts, and interrupt requests from peripheral functions data transfer controller ? three transfer modes : normal transfer, repeat transfer, and block transfer ? activated by interrupt requests (chain transfer enabled) i/o ports programmable i/o ports ? i/o pins: 117 ( 144- pin lqfp ), 140 ( 176- pin lfbga ) ? pull - up resistors: 40 ? open - drain outputs: 16 ? 5 - v tolerance: 10 timer 16- bit timer pulse unit ? (16 bits x 6 channels) x 2 units ? up to 16 pulse inputs and outputs ? select from among 7 or 8 counter - input clocks for each channel ? input capture/output compare function ? maximum of 15 - phase pwm output possible in pwm mode ? buffered operation, phase counting mode (two - phase encoder input), and cascaded operation (32 bits x 2 channels) settable for each channel ? ppg output trigger can be generated ? conversion start trigger for the a/d converter can be generated pr ogrammable pulse generator ? (4 bits x 4 groups) x 2 units ? provides pulse outputs by using the tpu output as a trigger ? maximum of 32 - bit pulse output possible 8- bit timer ? (8 bits x 2 channels) x 2 units ? select from among 8 clock sources (7 internal clocks and 1 external clock ) ? allows the output of pulse trains with a desired duty cycle or pwm signals ? cascading of 2 channels enables it to be used as a 16 - bit timer ? generation of trigger to start a/d converter conversion ? capable of generating baud rate clock f or sci5 and sci6 compare match timer ? (16 bits x 2 channels) x 2 units ? select from among 4 counter - input clocks
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 4 of 84 feb 20 , 201 3 watchdog timer ? 8 bits x 1 channel ? select from among 8 counter - input clocks ? switchable between watchdog timer mode and interval timer mode com munication function serial communication interface ? 7 channels ? serial communication mode : asynchronous, clock synchronous, and smart card interface ? on - chip baud rate generator allows any bit rate to be selected ? choice of lsb - first or msb - first transfer ? enab les average transfer rate clock input from tmr (sci5, sci6) i 2 c bus interface ? 2 channels ? communication format i 2 c bus format/smbus format master/slave selectable (for multi - master operation) ? maximum transfer rate: 1 mbps a/d converter ? 4 units (1 unit x 4 channels) ? 10- bit resolution ? conversion time: 1.0 s per channel (at 50 - mhz (pclk) operation) ? two kinds of operating modes single mode and scan mode (single scan mode or continuous scan mode) ? sample - and- hold function ? three types of a/d conversion start co nversion can be started by software, a conversion start trigger by the timer (tpu or tmr), or an external trigger signal. d/a converter ? 2 channels ? 10- bit resolution ? output voltage: 0 v to vrefh crc calculator ? crc code generation for arbitrary data length s in 8 - bit units ? one of three generating polynomials selectable x 8 + x 2 + x + 1 , x 16 + x 15 + x 2 + 1, x 16 + x 12 + x 5 + 1 ? crc code generation for lsb - first or msb - first communication selectable operating frequency 8 to 100 mhz power supply voltage v cc = pl lv cc = av cc = 3.0 to 3.6v, vrefh = 3.0 to av cc supply current 50 ma (typ.) (regular specifications ) operating temperature ? 20 to +85 c (regular specifications ), ? 40 to +85 c ( wide - range specifications) package 176- pin lfbga ( plbg0176ga -a) 144 - pin lqfp ( plqp0144ka - a )
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 5 of 84 feb 20 , 201 3 1.2 list of products table 1. 2 is the list of products, and figure 1.1 shows how to read the product part no. table 1.2 list of products part no. package rom capacity ram capacity data flash operating frequency (max.) r5f56108vnfp plqp0144 ka - a 2 m bytes 128 kbytes 32 kbytes 100 mhz r5f56108vdfp plqp0144ka -a 2 m bytes 128 kbytes 32 kbytes 100 mhz r5f56108 w nbg plbg0176ga - a 2 m bytes 128 kbytes 32 kbytes 100 mhz r5f56108wdbg plbg0176ga -a 2 m bytes 128 kbytes 32 kbytes 100 mhz r5f56107vnfp plqp 0144ka - a 1.5 m bytes 128 kbytes 32 kbytes 100 mhz r5f56107vdfp plqp0144ka -a 1.5 m bytes 128 kbytes 32 kbytes 100 mhz r5f56107 w nbg plbg0176ga - a 1.5 m bytes 128 kbytes 32 kbytes 100 mhz r5f56107wdbg plbg0176ga -a 1.5 m bytes 128 kbytes 32 kbytes 100 mhz r5f56 106vnfp plqp0144ka - a 1 m byte 128 kbytes 32 kbytes 100 mhz r5f56106vdfp plqp0144ka -a 1 m byte 128 kbytes 32 kbytes 100 mhz r5f56106 w nbg plbg0176ga - a 1 m byte 128 kbytes 32 kbytes 100 mhz r5f56106wdbg plbg0176ga -a 1 m byte 128 kbytes 32 kbytes 100 mhz r5f56 104vnfp plqp0144ka - a 768 kbytes 128 kbytes 32 kbytes 100 mhz r5f56104vdfp plqp0144ka -a 768 kbytes 128 kbytes 32 kbytes 100 mhz r5f56104 w nbg plbg0176ga - a 768 kbytes 128 kbytes 32 kbytes 100 mhz R5F56104WDBG plbg0176ga -a 768 kbytes 128 kbytes 32 kbytes 10 0 mhz
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 6 of 84 feb 20 , 201 3 5 56f 10 8 v n fp indicates the package. fp: lqfp bg: lfbga indicates the characteristic code. n: regular specifications d: wide-range specifications indicates the number of pins. v: 144 pins w: 176 pins indicates a renesas semiconductor product. indicates the type of memory. f: flash memory version indicates the rx600 series. indicates the rx610 group. r indicates a renesas mcu. indicates the rom capacity, ram capacity, and data flash capacity. 8: 2 mbytes/128 kbytes/32 kbytes 7: 1.5 mbytes/128 kbytes/32 kbytes 6: 1 mbyte/128 kbytes/32 kbytes 4: 768 kbytes/128 kbytes/32 kbytes figure 1.1 how to read the product part no.
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 7 of 84 feb 20 , 201 3 1.3 block diagram figure 1.2 shows a block diagram of the rx610 group. rom ram rx cpu dtc dmac external bus internal peripheral bus 2 internal peripheral bus 1 icu bsc a/d converter 4 channels (unit 3) a/d converter 4 channels (unit 2) a/d converter 4 channels (unit 1) a/d converter 4 channels (unit 0) tmr 2 channels (unit 1) tmr 2 channels (unit 0) tpu 6 channels (unit 1) tpu 6 channels (unit 0) ppg (unit 1) ppg (unit 0) d/a converter 2 channels cmt 2 channels (unit 1) sci 7 channels wdt riic 2 channels port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port a port b port c port d port e clock generation circuit data flash crc internal main bus 2 internal main bus 1 operand bus cmt 2 channels (unit 0) [legend] icu: interrupt control unit dtc: data transfer controller dmac: dma controller bsc: bus controller wdt: watchdog timer crc: crc (cyclic redundancy check) calculator sci: serial communications interfaces tpu: 16-bit timer pulse unit ppg: programmable pulse generator tmr: 8-bit timer cmt: compare match timer riic: i 2 c bus interface instruction bus port f port g port h * note: * ports f and h are not included in the 144-pin lqfp package. figure 1.2 block diagram
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 8 of 84 feb 20 , 201 3 1.4 pin assignments figure s 1. 3 and 1.4 show the pin assignment s of the 176- pin lfbga and the 14 4- pin lqfp , respectively . figure 1.5 (assistance diagram) shows the pin assignment the 14 4- pin lqfp . table s 1. 3 and 1.4 show the lists of pins and pin functions of the 176- pin lfbga and the 14 4- pin lqfp , respe ctively . pe2 pe1 pd5 vcc p61 pd0 pg1 p96 p92 vcc p45 p42 vrefh p05 p67 pe5 pe3 pd7 vss p62 pd2 pg3 bscanp p94 vss p47 p41 p03 p66 p02 pg5 pe7 pe6 pe4 p40 avss p01 p65 vss pg6 pg7 p00 emle wdtovf # vss pa1 pa0 pa2 mde vcl md 0 md1 pa5 pa4 pa6 p86 p85 xtal res# ph1 ph0 vss vss extal nmi vcc p70 vcc p71 p34 pf6 pf4 pf5 p74 p73 pb1 p33 p32 p30 p31 pb3 pb4 pb5 pf0 pf3 pf1 pf2 pb6 pc0 vss pc7 ph4 p51 p81 p83 p57 p37 p14 vss vcc p26 p27 pc1 pc2 ph2 p76 vss p50 p80 vss p56 p36 p12 p16 p20 p24 p25 vcc pc4 pc6 p77 vcc ph6 p52 vcc p54 p84 p11 p15 pllvcc p22 p23 pe0 pd6 pd4 p63 p60 pd1 pg2 p97 p93 p90 p46 p43 vrefl avcc p04 pc3 pc5 p75 ph3 ph5 ph7 p53 p82 p55 p35 p10 p13 pllvss p17 p21 b c d e f g h j k l m n p a r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b c d e f g h j k l m n p a r rx610group plbg0176ga-a (176-pin lfbga) (upper perspective view) pb7 pb2 p72 pb0 pa7 pa3 vcc p64 pd3 pg4 pg0 p95 p44 p91 figure 1.3 pin assignment of the 176- pin lfbga
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 9 of 84 feb 20 , 201 3 rx610 group plqp0144ka-a 144-pin lqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0/d8 pd6/d6 pd5/d5 pd4/d4 p64/cs4#-b p63/cs3#-a/cs7#-a p62/cs2#-a/cs6#-a p61/cs1#/cs2#-b/cs5#-a/cs6#-b/cs7#-b p60/cs0#/cs4#-a/cs5#-b pd3/d3 pd2/d2 pd1/d1 pd0/d0 p96/an14 p95/an13 p94/an12 p93/an11 p92/an10 p91/an9 vss p90/an8 vcc p47/an7/irq15-b p46/an6/irq14-b p45/an5/irq13-b p44/an4/irq12-b p43/an3/irq11-b p42/an2/irq10-b p41/an1/irq9-b vrefl p40/an0/irq8-b vrefh p05/tmo3/rxd4/irq13-a /tck pd 7/d7 p97/an15 avcc pc4/a20 pc6/a22/rxd5 /cs6#-d pc7/a23/txd5/cs4#-d/cs7#-d p75 p76/irq14-a p77 p50/wr0#/wr# p51/wr1#/bc1# p52/rd# p53/bclk p80 p81/trsync vcc vss p83 p54/trdata0 p55/trdata1 p56/trdata2 p57/wait#/trdata3 p84 p35/po13/tioca1/tiocb1/tclkc-a p36/po14/tioca2 p37/po15/tioca2/tiocb2/tclkd-a p10/irq0-b p11/sck2/irq1-b p12/rxd2/irq2-b p13/txd2/adtrg0#/irq3-b p14/tclka-b/sda1/irq4-b p15/tclkb-b/sck3/scl1/irq5-b pllvss p16/tclkc-b/rxd3/sda0/irq6-b pllvcc p20/po0/tioca3/tiocb3/tmri0/txd0 pc5/a21/sck5/cs5#-d p82/trclk p17/tclkd-b/txd3/scl0/adtrg1#/irq7-b pe1/d9 pe3/d11 pe4/d12 pe5/d13/irq5-a pe6/d14/irq6-a pe7/d15/irq7-a pa0/a0/bc0#/po16/tioca6 pa1/a1/po17/tioca6/tiocb6 pa2/a2/po18/tiocc6/tclke pa3 /a3/po19/tiocc6/tiocd6/tclkf pa 4/a4/po20/tioca7 pa5/a5/po21/tioca7/tiocb 7/tclkg pa6/a6/po22/tioca8 vss pb0/a8/po24/tioca9 vcc p70/cs3#-b/adtrg2# p71/cs4#-c/cs5#-c/cs6#-c/cs7#-c p72 p73 p74/adtrg3# pb1/a9/po25/tioca9/tiocb9 pb2/a10/po26/tiocc9 pb3/a11/po27/tiocc9/tiocd9 pb4/a12/po28/tioca10 pb5/a13/po29/tioca10/tiocb10 pb6/a14/po30/tioca11 pb7/a15/po31/tioca11/tiocb11 pc0/a16 pc1/a17 vss pc2/a18 pc3/a19 pe2/d10 pa7/a7/po23/tioca8/tiocb8/tclkh vcc p04/tmci3/txd4/irq12-a/tdi p67/da1 p66/da0 avss p02/tmo2/sck6/irq10-a/trst# p01/tmci2/rxd6/irq9-a p00/tmri2/txd6/irq8-a p65/irq15-a emle wdtovf#/tdo vss mde vcl md0 p86 p85 res# xtal vss extal vcc nmi p34/po12/tioca1/irq4-a p33/po11/tiocc0/tiocd0/tclkb-a/irq3-a p32/po10/tiocc0/tclka-a/irq2-a p31/po9/tioca0/ tiocb0/irq1-a p 30/po8/tioca0/irq0-a p27/po7/tioca5/tiocb5/sck1 p26/po6/tioca5/tmo1/txd1 p25/po5/tioca4/tmci1/rxd1 p24/po4/tioca4/tiocb4/tmri1 p23/po3/tiocc3/tiocd3 p21/po1/tioca3/tmci0/rxd0 p03/tmri3/sck4/irq11-a/tms md1 p22/po2/tiocc3/tmo0/sck0 figure 1.4 pin assignment of the 14 4- pin lqfp
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 10 of 84 feb 20 , 201 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0/d8 pd6/d6 pd5/d5 pd4/d4 p64/cs4#-b p63/cs3#-a/cs7#-a p62/cs2#-a/cs6#-a p61/cs1#/cs2#-b/cs5#-a/cs6#-b/cs7#-b p60/cs0#/cs4#-a/cs5#-b pd3/d3 pd2/d2 pd1/d1 pd0/d0 p96/an14 p95/an13 p94/an12 p93/an11 p92/an10 p91/an9 vss p90/an8 vcc p47/an7/irq15-b p46/an6/irq14-b p45/an5/irq13-b p44/an4/irq12-b p43/an3/irq11-b p42/an2/irq10-b p41/an1/irq9-b vrefl p40/an0/irq8-b vrefh p05/tmo3/rxd4/irq13-a/tck pd7/d7 p97/an15 avcc p04/tmci3/txd4/irq12-a/tdi p67/da1 p66/da0 p02/tmo2/sck6/irq10-a/trst# p01/tmci2/rxd6/irq9-a p00/tmri 2/txd6/irq8-a p 65/irq15-a emle wdtovf#/tdo vss mde vcl md0 p86 p85 res# xtal vss extal vcc nmi p34/po12/tioca1/irq4-a p33/po11/tiocc0/tiocd0/tclkb-a/irq3-a p32/po10/tiocc0/tclka-a/irq2-a p31/po9/tioca0/tiocb0/irq1-a p30/po8/tioca0/irq0- a p27/po7/tioca5/tiocb5/sck1 p26/po6/tioca5/tmo1/txd1 p25/po5/tioca4/tmci1/rxd1 p24/po4/tioca4/tiocb4/tmri1 p23/po3/tiocc3/tiocd3 p21/po1/tioca3/tmci0/rxd0 p03/tmri3/sck4/irq11-a/tms md1 p22/po2/tiocc3/tmo0/sck0 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 pc4/a20 pc6/a22/rxd5/cs6#-d pc7/a23/txd5/cs4#-d/cs7#-d p75 p76/irq14-a p77 p50/wr0#/wr# p51/wr1#/bc1# p52/rd# p53/bclk p80 p81/trsync vcc vss p83 p54/trdata0 p55/trdata1 p56/trdata2 p57/wait#/trdata3 p84 p35/po13/tioca1/tiocb1/tclkc-a p36/po14/tioca2 p37/po15/tioca2/tiocb2/tclkd-a p10/irq0-b p11/sck2/irq1-b p12/rxd2/irq2-b p13/txd2/adtrg0#/irq3-b p14/tclka-b/sda1/irq4-b p15/tclkb-b/sck3/scl1/irq5-b pllvss p16/tclkc-b/rxd3/sda0/irq6-b pllvcc p20/po0/tioca3/tiocb3/tmri0/txd0 pc5/a21/sck5/cs5#-d p82/trclk p17/tclkd-b/txd3/scl0/adtrg1#/irq7-b pe1/d9 pe3/d11 pe4/d12 pe5/d13/irq5-a pe6/d14 /irq6-a pe 7/d15/irq7-a pa0/a0/bc0#/po16/tioca6 pa1/a1/po17/tioca6/tiocb6 pa2/a2/po18/tiocc6/tclke pa3/a3/po19/tiocc6/tiocd6/tclkf pa4/a4/po20/tioca7 pa5/a5/po21/tioca7/tiocb7/tclkg pa6/a6/po22/tioca8 vss pb0/a8/po24/tioca9 vcc p70/cs3#-b/adtrg2# p71/cs4#-c/cs5#-c/cs6 #-c/cs7#-c p72 p73 p74/ adtrg3# pb1/a9/po25/tioca9/tiocb9 pb2/a10/po26/tiocc9 pb3/a11/po27/tiocc9/tiocd9 pb4/a12/po28/tioca10 pb5/a13/po29/tioca10/tiocb10 pb6/a14/po30/tioca11 pb7/a15/po31/tioca11/tiocb11 pc0/a16 pc1/a17 vss pc2/a18 pc3/a19 pe2/d10 pa7/a7/po23/tioca8/tiocb8/tclkh vcc rx610 group plqp0144ka-a 144-pin lqfp top view avss figure 1.5 pin assignment (assistance diagram) of the 14 4- pin lqf p
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 11 of 84 feb 20 , 201 3 table 1.3 list of pins and pin functions (176 - pin lfbga) pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 176- pin lfbga a1 p04 irq12 - a tmci3 txd4 tdi a2 avcc a3 vrefl a4 p43 irq11 - b an3 a5 p46 irq14 - b an6 a6 p90 an8 a7 p93 an11 a8 p97 an15 a9 pg2 a10 pd1 d1 a11 p60 cs0#/ cs4# - a/ cs5# - b a12 p63 cs3# - a/ cs7# - a a13 pd4 d4 a14 pd6 d6 a15 pe0 d8 b1 p67 da1 b2 p05 irq13 -a tmo3 rxd4 tck b3 vrefh b4 p42 irq10 - b an2 b5 p45 irq13 - b an5 b6 vcc b7 p92 an10 b8 p96 an14 b9 pg1 b10 pd0 d0 b11 p61 cs1#/ cs2# - b/ cs 5#- a/ cs6# - b/ cs7# -b b12 vcc b13 pd5 d5 b14 pe1 d9 b15 pe2 d10 c1 p02 irq10 - a tmo2 sck6 trst# c2 p66 da0 c3 p03 irq11 - a tmri3 sck4 tms c4 p41 irq9 - b an1 c5 p47 irq15 - b an7
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 12 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 176- pin lfbga c6 vss c7 p94 an12 c8 bscanp c9 pg3 c10 pd2 d2 c11 p62 cs2# - a/ cs6# - a c12 vss c13 pd7 d7 c14 pe3 d11 c15 pe5 irq5 - a d13 d1 p65 irq15 - a d2 p01 irq9 - a tmci2 rxd6 d3 avss d4 p40 irq8 - b an0 d5 p44 irq12 - b an4 d6 p91 an9 d7 p95 an13 d8 pg0 d9 pg4 d10 pd3 d3 d11 p64 cs4# - b d12 pe4 d12 d13 pe6 irq6 - a d14 d14 pe7 irq7 - a d15 d15 pg5 e1 vss e2 wdtovf# t do e3 emle e4 p00 irq8 - a tmri2 txd6 e12 vcc e13 pg7 e14 pg6 e15 vss f1 md1 f2 md0 f3 vcl f4 mde f12 pa3 a3 po19/ tiocc6/ tiocd6/ tclkf
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 13 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 176- pin lfbga f13 pa2 a2 po18/ tiocc6/ tclke f14 pa0 a0/bc0# po16/ tioca6 f15 pa1 a1 po17/ tioca6/ tiocb6 g1 res# g2 xtal g3 p85 g4 p86 g12 pa7 a7 po23/ tioca8/ tiocb8/ tclkh g13 pa6 a6 po22/ tioca8 g14 pa4 a4 po20/ tioca7 g15 pa5 a5 po2 1/ tioca7/ tiocb7/ tclkg h1 vcc h2 nmi h3 extal h4 vss h12 pb0 a8 po24/ tioca9 h13 vss h14 ph0 h15 ph1 j1 pf5 j2 pf4 j3 pf6 j4 p34 irq4 -a po12/ tioca1 j12 p72 j13 p71 cs4# - c/ cs5# - c/ cs6# - c/ cs7# - c j14 vcc
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 14 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 176- pin lfbga j15 p70 cs3# - b adtrg2# k1 p31 irq1 -a po9/ tioca0/ tiocb0 k2 p30 irq0 -a po8/ tioca0 k3 p32 irq2 -a po10/ tiocc0/ tclka - a k4 p33 irq3 -a po11/ tiocc0/ tiocd0/ tclkb - a k12 pb2 a10 po26/ tiocc9 k13 pb1 a9 po25/ tioca9/ tiocb9 k14 p73 k15 p74 adtrg3# l1 pf2 l2 pf1 l3 pf3 l4 pf0 l12 pb7 a15 po31/ tioca11/ tiocb11 l13 pb5 a13 po29/ tioca10/ tiocb10 l14 pb4 a12 po28/ tioca10 l15 pb3 a11 po27/ tiocc9/ tiocd9 m1 p27 po7/ tioca5/ tiocb5 sck1 m2 p26 po6/ tioca5/ tmo1 txd1 m3 vcc m4 vss m5 p14 irq4 - b tclka - b sda1
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 15 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 176- pin lfbga m6 p37 po15/ tioca2/ tiocb2/ tclkd - a m7 p 57 wait# trdata3 m8 p83 m9 p81 trsync m10 p51 wr1#/bc1# m11 ph4 m12 pc7 a23/ cs4# - d/ cs7# -d txd5 m13 vss m14 pc0 a16 m15 pb6 a14 po30/ tioca11 n1 p25 po5/ tioca4/ tmci1 rxd1 n2 p24 po4/ tioca4/ tiocb4/ tmri1 n3 p20 po0/ tioca3/ tiocb3/ tmri0 txd0 n4 p16 irq6 - b tclkc - b rxd3/sda0 n5 p12 irq2 - b rxd2 n6 p36 po14/ tioca2 n7 p56 trdata2 n8 vss n9 p80 n10 p50 wr0#/wr# n11 vss n12 p76 irq14 - a n13 ph2 n14 pc2 a18 n15 pc1 a17 p1 p23 po3/ tiocc3/ tiocd3
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 16 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 176- pin lfbga p2 p22 po2/ tiocc3/ tmo0 sck0 p3 pllvcc p4 p15 irq5 - b tclkb - b sck3/scl1 p5 p11 irq1 - b sck2 p6 p84 p7 p54 trda ta0 p8 vcc p9 p52 rd# p10 ph6 p11 v cc p12 p77 p13 pc6 a22/ cs6# - d rxd5 p14 pc4 a20 p15 vcc r1 p21 po1/ tioca3/ tmci0 rxd0 r2 p17 irq7 - b tclkd - b txd3/scl0 adtrg1# r3 pllvss r4 p 13 irq3 -b txd2 adtrg0# r5 p10 irq0 - b r6 p35 po13/ tioca1/ tiocb1/ tclkc - a r7 p55 trdata1 r8 p82 trclk r9 bclk p53 r10 ph7 r11 ph5 r12 ph3 r13 p75 r14 pc5 a21/ cs5# -d sck5 r15 pc3 a19
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 17 of 84 feb 20 , 201 3 table 1.4 list of pins and pin functions ( 14 4- pin lqfp ) pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 144- pin lqfp 1 p04 irq12 - a tmci3 txd4 tdi 2 p03 irq 11 -a tmri3 sck4 tms 3 p67 da1 4 p66 da0 5 avss 6 p02 irq10 -a tmo2 sck6 trst# 7 p01 irq9 - a tmci2 rxd6 8 p00 irq8 -a tmri2 txd6 9 p65 irq15 - a 10 emle 11 wdtovf# tdo 12 vss 13 mde 14 vcl 15 md1 16 md0 17 p86 18 p85 19 res# 20 xtal 21 vss 22 extal 23 vcc 24 nmi 25 p34 irq4 -a po12/ tioca1 26 p33 irq3 -a po11/ tiocc0/ tiocd0/ tclkb -a 27 p32 irq2 -a po10/ tiocc0/ tclka - a 28 p31 irq1 -a po9/ tioca0/ tiocb0 29 p30 irq0 -a po8/ tioca0 30 p27 po7/ tioca5/ tiocb5 sck1 31 p26 po6/ tioca5/ tmo1 txd1
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 18 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 144- pin lqfp 32 p25 po5/ tioca4/ tmci1 rxd1 33 p24 po4/ tioca4/ tiocb4/ tmri1 34 p23 po3/ tiocc3/ tiocd3 35 p22 po2/ tiocc3/ tmo0 sck0 36 p21 po1/ tioca3/ tmci0 rxd0 37 p20 po0/ tioca3/ tiocb3/ tmri0 txd0 38 p17 irq7 -b tclkd -b txd3/scl0 adtrg1# 39 pllvcc 40 p16 irq6 - b tclkc - b rxd3/sda0 4 1 pllvss 42 p15 irq5 - b tclkb - b sck3/scl1 43 p14 irq4 -b tclka -b sda1 44 p13 irq3 - b txd2 adtrg0# 45 p12 irq2 -b rxd2 46 p11 irq1 - b sck2 47 p10 irq0 -b 48 p37 po15/ tioca2/ tiocb2/ tclkd - a 49 p36 po14/ tioca2 50 p35 po13/ tioca1/ tiocb1/ tclkc - a 51 p84 52 p57 wait# trdata3 53 p56 trdata2 54 p55 trdata1
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 19 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 144- pin lqfp 55 p54 trdata0 56 p83 57 vss 58 p82 trclk 59 vcc 60 p81 trsync# 61 p80 62 bclk p53 63 p52 rd# 64 p51 wr1#/bc1# 65 p50 wr0#/wr# 66 p77 67 p76 irq14 - a 68 p75 69 pc7 a23/ cs4# - d/ cs7# - d txd5 70 pc6 a22/ cs6# - d rxd5 71 pc5 a21/ cs5# - d sck5 72 pc4 a20 73 pc3 a19 74 vcc 75 pc2 a18 76 vss 77 pc1 a17 78 pc0 a16 79 pb7 a15 po31/ tioca11/ tiocb11 80 pb6 a14 po30/ tioca11 81 pb5 a13 po29/ tioca10/ tiocb10 82 pb4 a12 po28/ tioca10 83 pb3 a11 p o27/ tiocc9/ tiocd9 84 pb2 a10 po26/ tiocc9
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 20 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 144- pin lqfp 85 pb1 a9 po25/ tioca9/ tiocb9 86 p74 adtrg3# 87 p73 88 p72 89 p71 cs4# - c/ cs5# - c/ cs6# - c/ cs7# - c 90 p70 cs3# - b adtrg2# 91 vcc 92 pb0 a8 po24/ tioca9 93 vss 94 pa7 a7 po23/ tioca8/ tiocb8/ tclkh 95 pa6 a6 po22/ tioca8 96 pa5 a5 po21/ tioca7/ tiocb7/ tclkg 97 pa4 a4 po20/ tioca7 98 pa3 a3 po19/ tiocc6/ tiocd6/ tclkf 99 pa2 a2 po18/ tiocc6/ tclke 100 pa1 a1 po17/ tioca6/ tiocb6 101 pa0 a0/bc0# po16/ tioca6 102 pe7 irq7 -a d15 103 pe6 irq6 - a d14 104 pe5 irq5 - a d13 105 pe4 d12 106 pe3 d11 107 pe2 d10
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 21 of 84 feb 20 , 201 3 pin no. power supply clock system control i/o port interrupt external bus timer communi - cation analog on - chip emulator 144- pin lqfp 108 pe1 d9 109 pe0 d8 110 pd7 d7 111 pd6 d6 112 pd5 d5 113 pd4 d4 114 p64 cs4# - b 115 p63 cs3# - a/ cs7# - a 116 p62 cs2# - a/ cs6# - a 117 p61 cs1#/ cs2# - b/ cs5# - a/ cs6# - b/ cs7# - b 118 p60 cs0#/ cs4# - a/ cs5# - b 119 pd3 d3 120 pd2 d2 121 pd1 d1 122 pd0 d0 123 p97 an15 124 p96 an14 125 p95 an13 126 p94 an12 127 p93 an11 128 p92 an10 129 p91 an9 130 vss 131 p90 an8 132 vcc 133 p47 irq15 -b an7 134 p46 irq14 - b an6 135 p45 irq13 -b an5 136 p44 irq12 - b an4 137 p43 irq11 - b an3 138 p42 irq10 - b an2 139 p41 irq9 -b an1 140 vrefl 141 p40 irq8 -b an0 142 vrefh 143 avcc 144 p05 irq13 - a tmo3 rxd4 tc k
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 22 of 84 feb 20 , 201 3 1.5 pin functions table 1. 5 lists the pin functions. table 1. 5 pin functions classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl input connect this pin to vss via a 0.1 - f cap acitor. the capacitor should be placed close to the pin. vss input ground pin. connect it to the system power supply (0 v). pllvcc input power supply pin for the pll circuit. connect it to the system power supply. pllvss input ground pin for the pll circuit clock xtal input pins for a crystal resonator. an external clock signal can be input through the extal pin. extal input b clk output outputs the system clock for external devices. operating mode control md0 , md1 , mde input pins for setting th e operating mode. the signal levels on these pins must not be changed during operation. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. emle input input pin to enable on- chip emulator signal. when the on - chip emulator is used, this pin should be driven high. when not used, it should be driven low. bscanp input input pin to enable boundary - scan signal. when this pin is driven high, the boundary scan is enabled. when the boundary scan is not us ed, this pin should be driven low. on - chip emulator trst# input on - chip emulator pins. when the emle pin is driven high, these pins are dedicated for the on - chip emulator. tms input tdi input tck input tdo output trclk output this pin outputs the clock for synchronization with the trace data. trsync output this pin indicates that output from the trdata0 to trdata3 pins is valid. trdata0 to trdata3 output these pins output the trace information. address bus a0 to a23 * 1 output output pins for the address data bus d0 to d15 i/o input and output pins for the bidirectional data bus
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 23 of 84 feb 20 , 201 3 classifications pin name i/o description bus control rd# output strobe signal which indicates that reading from the external address space is in progress. wr0# output strobe signal which indicates that the lower - order byte (d0 to d7) is valid in writing to the external address space , in byte strobe mode. wr1# output strobe signal which indicates that the higher - order byte (d8 to d15) is valid in writing to the external address space, in byte strobe mo de. wr# output strobe signal which indicates that writing to the external address space is in progress, in 1 - write strobe mode. bc0# * 1, * 2 output strobe signal which indicates that the lower - order byte (d0 to d7) is valid in access to the external add ress space, in 1 - write strobe mode. bc1# * 2 output strobe signal which indicates that the higher - order byte (d8 to d15) is valid in access to the external address space, in 1 - write strobe mode. cs0# , cs1# cs2# - a/cs2# -b cs3# - a/cs3# -b cs4# - a/cs4# - b/ cs4 #- c/cs4# -d cs5# - a/cs5# - b/ cs5# - c/cs5# -d cs6# - a/cs6# - b/ cs6# - c/cs6# -d cs7# - a/cs7# - b/ cs7# - c/cs7# - d output select signals for areas 0 to 7 wait# input requests wait cycles in access to the external address space
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 24 of 84 feb 20 , 201 3 classifications pin name i/o description interrupt nmi input non - maskable interrupt request signal irq0 - a/irq0 -b irq1 - a/irq1 -b irq2 - a/irq2 -b irq3 - a/irq3 -b irq4 - a/irq4 -b irq5 - a/irq5 -b irq6 - a/irq6 -b irq7 - a/irq7 -b irq8 - a/irq8 -b irq9 - a/irq9 -b irq10 - a/irq10 -b irq11 - a/irq11 -b irq12 - a/irq12 -b irq13 - a/irq13 -b irq14 - a/irq14 -b irq15 - a/irq15 - b input maskable request signals 16- bit timer pulse unit tioca0 , tiocb0 tiocc0 , tiocd0 i/o signals for tgra0 to tgrd0. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca1 , tiocb1 i/o signals for tgra1 and tgrb1. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca2 , tiocb2 i/o signals for tgra2 and tgrb2. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca3 , tiocb3 tiocc3 , tiocd3 i/o signal s for tgra3 to tgrd3. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca4 , tiocb4 i/o signals for tgra4 and tgrb4. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca5 , tioc b5 i/o signals for tgra5 and tgrb5. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca6 , tiocb6 tiocc6 , tiocd6 i/o signals for tgra6 to tgrd6. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca7 , tiocb7 i/o signals for tgra7 and tgrb7. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca8 , tiocb8 i/o signals for tgra8 and tgrb8. these pins are used as input capture inputs, output compa re outputs, or pwm outputs. tioca9 , tiocb9 tiocc9 , tiocd9 i/o signals for tgra9 to tgrd9. these pins are used as input capture inputs, output compare outputs, or pwm outputs. tioca10 , tiocb10 i/o signals for tgra10 and tgrb10. these pins are used as in put capture inputs, output compare outputs, or pwm outputs. tioca11 , tiocb11 i/o signals for tgra11 and tgrb11. these pins are used as input capture inputs, output compare outputs, or pwm outputs.
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 25 of 84 feb 20 , 201 3 classifications pin name i/o description 16- bit timer pulse unit tclka - a/tclka -b tclkb - a/tclkb -b tclkc - a/tclkc -b tclkd - a/tclkd -b tclke , tclkf tclkg , tclkh input input pins for external clock signals programmable pulse generator po0 to po31 output output pins for the pulse signals 8- bit timer tmo0 to tmo3 output output pins for the compare match sign als tmci0 to tmci3 input input pins for the external clock signals that drive for the counters tmri0 to tmri3 input input pins for the counter - reset signals watchdog timer wdtovf# output output pin for the counter - overflow signal in watchdog - timer mod e serial communication interface txd0 , txd1 , txd2 , txd3 , txd4 , txd5 , txd6 output output pins for data transmission rxd0 , rxd1 , rxd2 , rxd3 , rxd4 , rxd5 , rxd6 input input pins for data reception sck0 , sck1 , sck2 , sck3 , sck4 , sck5 , sck6 i/o input/output pins for clock signals i 2 c bus interface scl0 , scl1 i/o input/output pins for r iic clocks. bus can be directly driven by the nmos open drain output. sda0 , sda 1 i/o input/output pins for r iic data. bus can be directly driven by the nmos open drain output. a/d converter an0 to an15 input input pins for the analog signals to be processed by the a/d converter adtrg0# to adtrg3# input input pins for the external trigger signals that start the a/d conversion d/a converter da0 , da1 output output pins for the analog signals from the d/a converter
rx610 group 1 . overview r 01ds0097ej012 0 rev.1. 20 page 26 of 84 feb 20 , 201 3 classifications pin name i/o description analog power supply avcc input analog power supply pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. avss input ground pin for the a/d and d/a converters. connect this pin to the system power supply (0 v). v refh input reference power supply pin for the a/d and d/a converters. when the a/d and d/a converters are not in use, connect this pin to the system power supply. v refl input refer ence ground pin for the a/d and d/a converters. make sure to connect this pin to the analog reference power supply (0 v). when the a/d and d/a converters are not in use, connect this pin to the system power supply (0 v) . for details, see section 23.6.7, ranges of settings for analog power supply and other pins. i/o ports p00 to p05 i/o 6 - bit input/output pins p10 to p17 i/o 8 - bit input/output pins p20 to p27 i/o 8 - bit input/output pins p30 to p37 i/o 8 - bit input/output pins p40 to p47 i/o 8- bit input/output pins p50 to p57 i/o 8 - bit input/output pins. ( p53 is an input - only pin. ) p60 to p67 i/o 8 - bit input/output pins p70 to p77 i/o 8 - bit input/output pins p80 to p86 i/o 7 - bit input/output pins p90 to p97 i/o 8 - bit input/output pins pa0 t o pa7 i/o 8- bit input/output pins pb0 to pb7 i/o 8 - bit input/output pins pc0 to pc7 i/o 8 - bit input/output pins pd0 to pd7 i/o 8 - bit input/output pins pe0 to pe7 i/o 8 - bit input/output pins pf0 to pf6 i/o 7 - bit input/output pins pg0 to pg7 i/o 8- bit input/output pins ph0 to ph7 i/o 8 - bit input/output pins note 1: the a0 and bc0# pin functions are multiplexed on the same pin: the a0 pin is valid in byte - write mode and the bc0# pin becomes valid in single write - strobe mode. the setting for an e ight - bit external bus width is prohibited in single write - strobe mode. for other multiplexed pin functions, refer to section 14, i/o ports. note 2: the bc0# and bc1# signals are valid in both reading and writing .
rx610 group 2. cpu r 01ds0097ej012 0 rev.1. 20 page 27 of 84 f eb 20 , 20 13 2. cpu t he rx cpu has sixteen general - purpose registers, nine control registers, and one accumulator used for dsp instructions . note: * the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) * general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator) figure 2.1 register set of the cpu
rx610 group 2. cpu r 01ds0097ej012 0 rev.1. 20 page 28 of 84 f eb 20 , 20 13 2.1 general - purpose registers ( r0 to r15 ) this cpu has sixteen general - purpose registers (r0 to r15). r1 to r15 can be used as data registers o r address registers. r0, a general - purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by the value of the stack pointer select bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer ( isp )/user stack pointer ( usp ) the stack pointer (sp) can be either of two types, the interrupt stack pointer (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack pointer select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences and instructions entailin g stack manipulation. (2) interrupt table register ( intb ) the interrupt table register (intb) specifies the address where the relocatable vector table starts. (3) program counter ( pc ) the program counter (pc) indicates the address of the instruction being executed . (4) processor status word ( psw ) the processor status word (psw) indicates results of instruction execution or the state of the cpu. (5) backup pc (bpc ) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc. (6) backup psw (bpsw ) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw) are saved i n the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register ( fintv ) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv specifies a branch destination addres s when a fast interrupt has been generated.
rx610 group 2. cpu r 01ds0097ej012 0 rev.1. 20 page 29 of 84 f eb 20 , 20 13 (8) floating - point status word ( fpsw ) the floating - point status word (fpsw) indicates the results of floating - point operations. when an exception handling enable bit (ej) enables the exception handling (ej = 1), the corresponding cj flag indicates the source of the exception within the exception handling routine. if the exception handling is masked (ej = 0), check the fj flag at the end of a series of processing whether an exception is generated or not. the fj flag is the accumulation type flag (j = x, u, z, o, or v) . (9) accumulator (acc) the accumulator (acc) is a 64 - bit register used for dsp instructions. the accumulator is also used for the multiply and multiply - and - accumulate instructions; emul, emulu, fmul, mul, an d rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for writing to the accumulator. the mvtachi and mvtaclo instructions write data to the higher - order 32 bits (bits 63 to 32) and the lower - order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from the accumulator. the mvfachi and mvfacmi instructions read data from the higher - order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
rx610 group 3 . address space r 01ds0097ej012 0 rev.1. 20 page 30 of 84 feb 20 , 201 3 3. address space 3.1 address space this mcu has a 4 - gbyte address space, consisting of the range of addresses from 0000 0000h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is possible, and this contains both program and data areas. f igure s 3 .1 to 3 .4 show the memory map s in the respective operating mode s of each product . accessible areas will differ according to the operating mode and states of control bits. reserved area* 1 reserved area* 1 reserved area* 1 on-chip ram external address space reserved area* 1 peripheral i/o registers reserved area* 1 reserved area* 1 external address space on-chip ram reserved area* 1 on-chip rom (program rom) (read only) peripheral i/o registers on-chip rom (data flash) on-chip rom (program rom) (write only) on-chip rom (user boot) (read only) on-chip rom (fcu firmware)* 3 (read only) reserved area* 1 reserved area* 1 fcu ram area* 3 reserved area* 1 peripheral i/o registers reserved area* 1 peripheral i/o registers reserved area* 1 external address space reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 notes: 1. a reserved area should not be accessed. 2. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. for details on the fcu, see section 26, rom (flash memory for code storage) and section 27, data flash (flash memory for data storage) in the users manual: hardware. 0000 0000h 0008 0000h ffff ffffh single-chip mode* 2 on-chip ram on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) ffe0 0000h ff7f c000h on-chip rom (user boot) (read only) on-chip rom (fcu firmware)* 3 (read only) feff e000h ff00 0000h fcu ram area* 3 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode 0010 0000h 0010 8000h 0080 0000h 0100 0000h 0800 0000h ffe0 0000h ff7f c000h feff e000h ff00 0000h 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode 0010 0000h 0100 0000h 0800 0000h ff00 0000h 0002 0000h ff80 0000h ff80 0000h 00e0 0000h 00e0 0000h peripheral i/o registers figure 3 .1 memory map of the r5f56108
rx610 group 3 . address space r 01ds0097ej012 0 rev.1. 20 page 31 of 84 feb 20 , 201 3 reserved area* 1 reserved area* 1 reserved area* 1 on-chip ram external address space reserved area* 1 peripheral i/o registers reserved area* 1 reserved area* 1 external address space on-chip ram reserved area* 1 on-chip rom (program rom) (read only) peripheral i/o registers on-chip rom (data flash) on-chip rom (program rom) (write only) on-chip rom (user boot) (read only) on-chip rom (fcu firmware)* 3 (read only) reserved area* 1 reserved area* 1 fcu ram area* 3 reserved area* 1 peripheral i/o registers reserved area* 1 peripheral i/o registers reserved area* 1 external address space reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 reserved area * 1 reserved area* 1 reserved area* 1 0000 0000h 0008 0000h ffff ffffh single-chip mode* 2 on-chip ram on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) ffe8 0000h ff7f c000h on-chip rom (user boot) (read only) on-chip rom (fcu firmware)* 3 (read only) feff e000h ff00 0000h fcu ram area* 3 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode 0010 0000h 0010 8000h 0080 0000h 0100 0000h 0800 0000h ffe8 0000h ff7f c000h feff e000h ff00 0000h 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode 0010 0000h 0100 0000h 0800 0000h ff00 0000h 0002 0000h ff80 0000h ff80 0000h 00e8 0000h 00e8 0000h peripheral i/o registers notes: 1. a reserved area should not be accessed. 2. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. for details on the fcu, see section 26, rom (flash memory for code storage) and section 27, data flash (flash memory for data storage) in the users manual: hardware. figure 3 .2 memory map of the r5f56107
rx610 group 3 . address space r 01ds0097ej012 0 rev.1. 20 page 32 of 84 feb 20 , 201 3 reserved area * 1 reserved area * 1 reserved area * 1 on-chip ram external address space reserved area * 1 peripheral i/o registers reserved area * 1 reserved area * 1 external address space on-chip ram reserved area * 1 on-chip rom (program rom) (read only) peripheral i/o registers on-chip rom (data flash) on-chip rom (program rom) (write only) on-chip rom (user boot) (read only) on-chip rom (fcu firmware) * 3 (read only) reserved area * 1 reserved area * 1 fcu ram area* 3 reserved area * 1 peripheral i/o registers reserved area * 1 peripheral i/o registers reserved area * 1 external address space reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 0000 0000h 0008 0000h ffff ffffh single-chip mode * 2 on-chip ram on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) fff0 0000h ff7f c000h on-chip rom (user boot) (read only) on-chip rom (fcu firmware) * 3 (read only) feff e000h ff00 0000h fcu ram area* 3 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode 0010 0000h 0010 8000h 0080 0000h 0100 0000h 0800 0000h fff0 0000h ff7f c000h feff e000h ff00 0000h 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode 0010 0000h 0100 0000h 0800 0000h ff00 0000h 0002 0000h ff80 0000h ff80 0000h 00f0 0000h 00f0 0000h peripheral i/o registers notes: 1. a reserved area should not be accessed. 2. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. for details on the fcu, see section 26, rom (flash memory for code storage) and section 27, data flash (flash memory for data storage) in the users manual: hardware. figure 3 .3 memory map of the r5f56106
rx610 group 3 . address space r 01ds0097ej012 0 rev.1. 20 page 33 of 84 feb 20 , 201 3 reserved area * 1 reserved area * 1 reserved area * 1 on-chip ram external address space reserved area * 1 peripheral i/o registers reserved area * 1 reserved area * 1 external address space on-chip ram reserved area * 1 on-chip rom (program rom) (read only) peripheral i/o registers on-chip rom (data flash) on-chip rom (program rom) (write only) on-chip rom (user boot) (read only) on-chip rom (fcu firmware)* 3 (read only) reserved area * 1 reserved area * 1 fcu ram area* 3 reserved area * 1 peripheral i/o registers reserved area * 1 peripheral i/o registers reserved area * 1 external address space reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 reserved area * 1 0000 0000h 0008 0000h ffff ffffh single-chip mode * 2 on-chip ram on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) fff4 0000h ff7f c000h on-chip rom (user boot) (read only) on-chip rom (fcu firmware)* 3 (read only) feff e000h ff00 0000h fcu ram area* 3 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode 0010 0000h 0010 8000h 0080 0000h 0100 0000h 0800 0000h fff4 0000h ff7f c000h feff e000h ff00 0000h 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0002 0000h 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode 0010 0000h 0100 0000h 0800 0000h ff00 0000h 0002 0000h ff80 0000h ff80 0000h 00f4 0000h 00f4 0000h peripheral i/o registers notes: 1. a reserved area should not be accessed. 2. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. for details on the fcu, see section 26, rom (flash memory for code storage) and section 27, data flash (flash memory for data storage) in the users manual: hardware. figure 3 .4 memory map of the r5f56104
rx610 group 3 . address space r 01ds0097ej012 0 rev.1. 20 page 34 of 84 feb 20 , 201 3 3.2 external address space the external address space is divided into up to 8 areas, ea ch corresponding to the csi# signal output from a csi# ( i = 0 to 7) pin. figure 4.5 shows the address ranges corresponding to the individual csi# signals (csi areas, i = 0 to 7) in on- chip rom disabled external extended mode . 0000 0000h 0008 0000h on-chip ram external address space reserved area * 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h reserved area 0002 0000h reserved area external address space* 0100 0000h 0200 0000h 0300 0000h 0400 0000h 0500 0000h 0600 0000h 0700 0000h cs7 (16 mbytes) 01ff ffffh 02ff ffffh 03ff ffffh 04ff ffffh 05ff ffffh 06ff ffffh 07ff ffffh cs6 (16 mbytes) cs5 (16 mbytes) cs4 (16 mbytes) cs3 (16 mbytes) cs2 (16 mbytes) cs1 (16 mbytes) ffff ffffh ffff ffffh ff00 0000h cs0 (16 mbytes) note: * cs0 area is disabled in on-chip rom enabled external extended mode. in this mode, the address space for addresses above 0800 0000h is as shown in figure 4.1. figure 3 .5 correspondence between external address spaces and csi areas ( in on - chip rom disabled external extended mode )
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 35 of 84 feb 20 , 201 3 4. i/o registers table 4 .1 list of i/o registers (address order) address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0002h system mode status register mdsr 16 16 3 iclk 0008 0006h system system control register 0 syscr0 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system mo dule stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 i clk 0008 1300h bsc bus error source clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitor enable register beren 8 8 2 iclk 0008 1306h bsc bus error interrupt enable register berie 8 8 2 iclk 0008 2000h dmac0 dma current transfer source addr ess register dmcsa 32 32 4 to 5 iclk 0008 2004h dmac0 dma current transfer destination address register dmcda 32 32 4 to 5 iclk 0008 2008h dmac0 dma current transfer byte count register dmcbc 32 32 4 to 5 iclk 0008 200ch dmac0 dma mode register dmmod 32 32 4 to 5 iclk 0008 2010h dmac1 dma current transfer source address register dmcsa 32 32 4 to 5 iclk 0008 2014h dmac1 dma current transfer destination address register dmcda 32 32 4 to 5 iclk 0008 2018h dmac1 dma current transfer byte count register dmcbc 32 32 4 to 5 iclk 0008 201ch dmac1 dma mode register dmmod 32 32 4 to 5 iclk 0008 2020h dmac2 dma current transfer source address register dmcsa 32 32 4 to 5 iclk 0008 2024h dmac2 dma current transfer destination address register dmcda 32 32 4 to 5 iclk 0008 2028h dmac2 dma current transfer byte count register dmcbc 32 32 4 to 5 iclk 0008 202ch dmac2 dma mode register dmmod 32 32 4 to 5 iclk 0008 2030h dmac3 dma current transfer source address register dmcsa 32 32 4 to 5 iclk 0008 2034h dmac3 dma current transfer destination address register dmcda 32 32 4 to 5 iclk 0008 2038h dmac3 dma current transfer byte count register dmcbc 32 32 4 to 5 iclk 0008 203ch dmac3 dma mode register dmmod 32 32 4 to 5 iclk 0008 2200h dmac0 dma reload transfer sour ce address register dmrsa 32 32 4 to 5 iclk * 8 0008 2204h dmac0 dma reload transfer destination address register dmrda 32 32 4 to 5 iclk * 8 0008 2208h dmac0 dma reload transfer byte count register dmrbc 32 32 4 to 5 iclk * 8 0008 2210h dmac1 dma reload transfer source address register dmrsa 32 32 4 to 5 iclk * 8 0008 2214h dmac1 dma reload transfer destination address register dmrda 32 32 4 to 5 iclk * 8 0008 2218h dmac1 dma reload transfer byte count register dmrbc 32 32 4 to 5 iclk * 8 0008 2220h dmac2 dma reload transfer source address register dmrsa 32 32 4 to 5 iclk * 8 0008 2224h dmac2 dma reload transfer destination address register dmrda 32 32 4 to 5 iclk * 8 0008 2228h dmac2 dma reload transfer byte count register dmrbc 32 32 4 to 5 iclk * 8 0008 2230h dmac3 dma reload transfer source address register dmrsa 32 32 4 to 5 iclk * 8 0008 2234h dmac3 dma reload transfer destination address register dmrda 32 32 4 to 5 iclk * 8 0008 2238h dmac3 dma reload transfer byte count register dmrbc 32 32 4 to 5 i clk * 8
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 36 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 2400h dmac0 dma control register a dmcra 32 32 3 iclk 0008 2404h dmac0 dma control register b dmcrb 8 8 3 iclk 0008 2405h dmac0 dma control register c dmcr c 8 8 3 iclk 0008 2406h dmac0 dma control register d dmcr d 8 8 3 iclk 0008 2407h dma c0 dma control register e dmcr e 8 8 3 iclk 0008 2408h dmac1 dma control register a dmcra 32 32 3 iclk 0008 240ch dmac1 dma control register b dmcrb 8 8 3 iclk 0008 240dh dmac 1 dma control register c dmcr c 8 8 3 iclk 0008 240eh dmac 1 dma control registe r d dmcr d 8 8 3 iclk 0008 240fh dmac 1 dma control register e dmcr e 8 8 3 iclk 0008 2410h dmac2 dma control register a dmcra 32 32 3 iclk 0008 2414h dmac2 dma control register b dmcrb 8 8 3 iclk 0008 2415h dmac 2 dma control register c dmcr c 8 8 3 iclk 0008 2416h dmac 2 dma control register d dmcr d 8 8 3 iclk 0008 2417h dmac 2 dma control register e dmcr e 8 8 3 iclk 0008 2418h dmac3 dma control register a dmcra 32 32 3 iclk 0008 241ch dmac3 dma control register b dmcrb 8 8 3 iclk 0008 241dh dmac 3 dma c ontrol register c dmcr c 8 8 3 iclk 0008 241eh dmac 3 dma control register d dmcr d 8 8 3 iclk 0008 241fh dmac 3 dma control register e dmcr e 8 8 3 iclk 0008 2502h dmac common dma start control register dmscnt 8 8 3 iclk 0008 250bh dmac common dma interrup t control register dmicnt 8 8 3 iclk 0008 2517h dmac common dma transfer end detect register dmedet 8 8 3 iclk 0008 251bh dmac common dma arbitration status register dmasts 8 8 3 iclk 0008 300 2h bsc cs0 mode register cs0mod 16 16 1 to 2 bclk * 7 0008 30 04h bsc cs0 wait control register 1 cs0wcnt1 32 32 1 to 2 bclk * 7 0008 3008h bsc cs0 wait control register 2 cs0wcnt2 32 32 1 to 2 bclk * 7 0008 301 2 h bsc cs1 mode register cs1mod 16 16 1 to 2 bclk * 7 0008 3014h bsc cs1 wait control register 1 cs1wcnt1 32 32 1 to 2 bclk * 7 0008 3018h bsc cs1 wait control register 2 cs1wcnt2 32 32 1 to 2 bclk * 7 0008 302 2 h bsc cs2 mode register cs2mod 16 16 1 to 2 bclk * 7 0008 3024h bsc cs2 wait control register 1 cs2wcnt1 32 32 1 to 2 bclk * 7 0008 3028h bsc cs2 wait c ontrol register 2 cs2wcnt2 32 32 1 to 2 bclk * 7 0008 303 2 h bsc cs3 mode register cs3mod 16 16 1 to 2 bclk * 7 0008 3034h bsc cs3 wait control register 1 cs3wcnt1 32 32 1 to 2 bclk * 7 0008 3038h bsc cs3 wait control register 2 cs3wcnt2 32 32 1 to 2 bclk * 7 0008 304 2 h bsc cs4 mode register cs4mod 16 16 1 to 2 bclk * 7 0008 3044h bsc cs4 wait control register 1 cs4wcnt1 32 32 1 to 2 bclk * 7 0008 3048h bsc cs4 wait control register 2 cs4wcnt2 32 32 1 to 2 bclk * 7 0008 305 2 h bsc cs5 mode register cs5mod 16 16 1 to 2 bclk * 7 0008 3054h bsc cs5 wait control register 1 cs5wcnt1 32 32 1 to 2 bclk * 7 0008 3058h bsc cs5 wait control register 2 cs5wcnt2 32 32 1 to 2 bclk * 7 0008 306 2h bsc cs6 mode register cs6mod 16 16 1 to 2 bclk * 7 0008 3064h bsc cs6 wait con trol register 1 cs6wcnt1 32 32 1 to 2 bclk * 7 0008 3068h bsc cs6 wait control register 2 cs6wcnt2 32 32 1 to 2 bclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 37 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 307 2 h bsc cs7 mode register cs7mod 16 16 1 to 2 bclk * 7 0008 3074h bsc cs7 wait control register 1 cs7wcnt1 32 32 1 to 2 bclk * 7 0008 3078h bsc cs7 wait control register 2 cs7wcnt2 32 32 1 to 2 bclk * 7 0008 380 2 h bsc cs0 control register cs0cnt 16 16 1 to 2 bclk * 7 0008 380 ah bsc cs0 recovery cycle register cs0rec 16 16 1 to 2 bclk * 7 0008 381 2 h bsc cs1 control register cs1cnt 1 6 16 1 to 2 bclk * 7 0008 381 ah bsc cs1 recovery cycle register cs1rec 16 16 1 to 2 bclk * 7 0008 382 2 h bsc cs2 control register cs2cnt 16 16 1 to 2 bclk * 7 0008 382 ah bsc cs2 recovery cycle register cs2rec 16 16 1 to 2 bclk * 7 0008 383 2 h bsc cs3 control register cs3cnt 16 16 1 to 2 bclk * 7 0008 383 ah bsc cs3 recovery cycle register cs3rec 16 16 1 to 2 bclk * 7 0008 384 2 h bsc cs4 control register cs4cnt 16 16 1 to 2 bclk * 7 0008 384 a h bsc cs4 recovery cycle register cs4rec 16 16 1 to 2 bclk * 7 0008 385 2 h bsc cs5 control register cs5cnt 16 16 1 to 2 bclk * 7 0008 385 ah bsc cs5 recovery cycle register cs5rec 16 16 1 to 2 bclk * 7 0008 386 2 h bsc cs6 control register cs6cnt 16 16 1 to 2 bclk * 7 0008 386 ah bsc cs6 recovery cycle register cs6rec 16 16 1 to 2 bclk * 7 0008 387 2 h bsc cs7 control register cs7cnt 16 16 1 to 2 bclk * 7 0008 387 a h bsc cs7 recovery cycle register cs7rec 16 16 1 to 2 bclk * 7 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7015h icu interrupt request register 021 ir021 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7048h icu interrupt request register 072 ir072 8 8 2 iclk 0008 7049h icu interrupt request register 073 ir073 8 8 2 iclk 0008 704ah icu interrupt request register 074 ir074 8 8 2 iclk 0008 704bh icu interrupt request register 075 ir075 8 8 2 iclk 0008 704ch icu interrupt request register 076 ir076 8 8 2 iclk 0008 704dh icu interrupt request register 077 ir077 8 8 2 iclk 0008 704eh icu interrupt request register 078 ir078 8 8 2 iclk 0008 704fh icu interrupt request register 079 ir079 8 8 2 iclk 0008 7060h icu interrupt request register 096 ir096 8 8 2 iclk 0008 7062h icu interrupt request register 098 ir098 8 8 2 iclk 0008 7063h icu interrupt request register 099 ir099 8 8 2 iclk
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 38 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 7064h icu interrupt request register 100 ir100 8 8 2 iclk 0008 7065h icu interrupt request register 101 ir101 8 8 2 iclk 0008 7068h icu interrupt request register 104 ir104 8 8 2 iclk 0008 7069h icu interrupt request register 105 ir105 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 706bh icu interrupt request register 107 ir107 8 8 2 iclk 0008 706ch icu interrupt request register 108 ir108 8 8 2 iclk 0008 706fh icu interrupt request register 111 ir111 8 8 2 iclk 0008 7070h icu interrupt request register 112 ir112 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2 iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2 iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2 iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2 iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2 iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2 iclk 0008 7098h icu interrupt request register 152 ir152 8 8 2 iclk 0008 709ah icu interrupt request register 154 ir154 8 8 2 iclk 0008 709bh icu interrupt request register 155 ir155 8 8 2 iclk 0008 709ch icu interrupt request register 156 ir156 8 8 2 iclk 0008 709dh icu interrupt request register 157 ir157 8 8 2 iclk 0008 709eh icu interrupt request register 158 ir158 8 8 2 iclk 0008 709fh icu interrupt request register 159 ir159 8 8 2 iclk
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 39 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 70a0h icu interrupt request register 160 ir160 8 8 2 iclk 0008 70a1h icu interrupt request register 161 ir161 8 8 2 iclk 0008 70a2h icu interrupt request register 162 ir162 8 8 2 iclk 0008 70a5h icu interrupt request register 165 ir165 8 8 2 iclk 0008 70a6h icu interrupt request register 166 ir166 8 8 2 iclk 0008 70a7h icu interrupt request register 167 ir167 8 8 2 iclk 0008 70a8h icu interrupt request register 168 ir168 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70e6h icu interrupt request register 230 ir230 8 8 2 iclk 0008 70e7h icu interrupt request register 231 ir231 8 8 2 iclk 0008 70e8h icu interrupt request register 232 ir232 8 8 2 iclk 0008 70e9h icu interrupt request register 233 ir233 8 8 2 iclk
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 40 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f 6h icu interrupt request register 24 6 ir24 6 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 70f a h icu interrupt request register 2 50 ir2 50 8 8 2 iclk 0008 70fbh icu interrupt request register 251 ir251 8 8 2 iclk 0008 70fch icu interrupt request register 252 ir252 8 8 2 iclk 0008 70fdh icu interrupt request register 253 ir253 8 8 2 iclk 0008 71 1ch icu interrupt request destination setting register 028 iselr028 8 8 2 iclk 0008 7 1 1dh icu interru pt request destination setting register 029 iselr029 8 8 2 iclk 0008 7 1 1eh icu interrupt request destination setting register 030 iselr030 8 8 2 iclk 0008 7 1 1fh icu interrupt request destination setting register 031 iselr031 8 8 2 iclk 0008 71 40h icu in terrupt request destination setting register 064 iselr064 8 8 2 iclk 0008 7 1 41h icu interrupt request destination setting register 065 iselr065 8 8 2 iclk 0008 71 42h icu interrupt request destination setting register 066 iselr066 8 8 2 iclk 0008 7 1 43h i cu interrupt request destination setting register 067 iselr067 8 8 2 iclk 0008 71 44h icu interrupt request destination setting register 068 iselr068 8 8 2 iclk 0008 7 1 45h icu interrupt request destination setting register 069 iselr069 8 8 2 iclk 0008 71 46h icu interrupt request destination setting register 070 iselr070 8 8 2 iclk 0008 7 1 47h icu interrupt request destination setting register 071 iselr071 8 8 2 iclk 0008 71 48h icu interrupt request destination setting register 072 iselr072 8 8 2 iclk 00 08 7 1 49h icu interrupt request destination setting register 073 iselr073 8 8 2 iclk 0008 7 1 4ah icu interrupt request destination setting register 074 iselr074 8 8 2 iclk 0008 7 1 4bh icu interrupt request destination setting register 075 iselr075 8 8 2 icl k 0008 71 4ch icu interrupt request destination setting register 076 iselr076 8 8 2 iclk 0008 7 1 4dh icu interrupt request destination setting register 077 iselr077 8 8 2 iclk 0008 71 4eh icu interrupt request destination setting register 078 iselr078 8 8 2 iclk 0008 7 1 4fh icu interrupt request destination setting register 079 iselr079 8 8 2 iclk 0008 7 1 62h icu interrupt request destination setting register 098 iselr098 8 8 2 iclk 0008 7 1 63h icu interrupt request destination setting register 099 iselr099 8 8 2 iclk 0008 71 64h icu interrupt request destination setting register 100 iselr100 8 8 2 iclk 0008 7 1 65h icu interrupt request destination setting register 101 iselr101 8 8 2 iclk 0008 71 68h icu interrupt request destination setting register 104 ise lr104 8 8 2 iclk 0008 7 1 69h icu interrupt request destination setting register 105 iselr105 8 8 2 iclk 0008 71 6ah icu interrupt request destination setting register 106 iselr106 8 8 2 iclk 0008 7 1 6bh icu interrupt request destination setting register 10 7 iselr107 8 8 2 iclk 0008 71 6fh icu interrupt request destination setting register 111 iselr111 8 8 2 iclk
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 41 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 7 1 70h icu interrupt request destination setting register 112 iselr112 8 8 2 iclk 0008 7 1 75h icu interrupt request destination setting regist er 117 iselr117 8 8 2 iclk 0008 71 76h icu interrupt request destination setting register 118 iselr118 8 8 2 iclk 0008 7 1 7ah icu interrupt request destination setting register 122 iselr122 8 8 2 iclk 0008 71 7bh icu interrupt request destination setting r egister 123 iselr123 8 8 2 iclk 0008 7 1 7ch icu interrupt request destination setting register 124 iselr124 8 8 2 iclk 0008 71 7dh icu interrupt request destination setting register 125 iselr125 8 8 2 iclk 0008 7 1 7fh icu interrupt request destination sett ing register 127 iselr127 8 8 2 iclk 0008 71 80h icu interrupt request destination setting register 128 iselr128 8 8 2 iclk 0008 7 1 85h icu interrupt request destination setting register 133 iselr133 8 8 2 iclk 0008 71 86h icu interrupt request destination setting register 134 iselr134 8 8 2 iclk 0008 7 1 8ah icu interrupt request destination setting register 138 iselr138 8 8 2 iclk 0008 7 1 8bh icu interrupt request destination setting register 139 iselr139 8 8 2 iclk 0008 7 1 8ch icu interrupt request destin ation setting register 140 iselr140 8 8 2 iclk 0008 71 8dh icu interrupt request destination setting register 141 iselr141 8 8 2 iclk 0008 7 1 91h icu interrupt request destination setting register 145 iselr145 8 8 2 iclk 0008 71 92h icu interrupt request d estination setting register 146 iselr146 8 8 2 iclk 0008 7 1 97h icu interrupt request destination setting register 151 iselr151 8 8 2 iclk 0008 7 1 98h icu interrupt request destination setting register 152 iselr152 8 8 2 iclk 0008 7 1 9ch icu interrupt requ est destination setting register 156 iselr156 8 8 2 iclk 0008 71 9dh icu interrupt request destination setting register 157 iselr157 8 8 2 iclk 0008 7 1 9eh icu interrupt request destination setting register 158 iselr158 8 8 2 iclk 0008 71 9fh icu interrupt request destination setting register 159 iselr159 8 8 2 iclk 0008 7 1 a1h icu interrupt request destination setting register 161 iselr161 8 8 2 iclk 0008 71 a2h icu interrupt request destination setting register 162 iselr162 8 8 2 iclk 0008 7 1 a7h icu inte rrupt request destination setting register 167 iselr167 8 8 2 iclk 0008 71 a8h icu interrupt request destination setting register 168 iselr168 8 8 2 iclk 0008 7 1 aeh icu interrupt request destination setting register 174 iselr174 8 8 2 iclk 0008 71 afh icu interrupt request destination setting register 175 iselr175 8 8 2 iclk 0008 7 1 b1h icu interrupt request destination setting register 177 iselr177 8 8 2 iclk 0008 7 1 b2h icu interrupt request destination setting register 178 iselr178 8 8 2 iclk 0008 7 1 b4 h icu interrupt request destination setting register 180 iselr180 8 8 2 iclk 0008 71 b5h icu interrupt request destination setting register 181 iselr181 8 8 2 iclk 0008 7 1 b7h icu interrupt request destination setting register 183 iselr183 8 8 2 iclk 0008 71 b8h icu interrupt request destination setting register 184 iselr184 8 8 2 iclk 0008 7 1 c6h icu interrupt request destination setting register 198 iselr198 8 8 2 iclk 0008 7 1 c7h icu interrupt request destination setting register 199 iselr199 8 8 2 iclk 0008 7 1 c8h icu interrupt request destination setting register 200 iselr200 8 8 2 iclk 0008 71 c9h icu interrupt request destination setting register 201 iselr201 8 8 2 iclk 0008 7 1 d7h icu interrupt request destination setting register 215 iselr215 8 8 2 iclk 0008 71 d8h icu interrupt request destination setting register 216 iselr216 8 8 2 iclk 0008 7 1 dbh icu interrupt request destination setting register 219 iselr219 8 8 2 iclk 0008 71 dch icu interrupt request destination setting register 220 iselr220 8 8 2 iclk 0008 7 1 dfh icu interrupt request destination setting register 223 iselr223 8 8 2 iclk 0008 71 e0h icu interrupt request destination setting register 224 iselr224 8 8 2 iclk
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 42 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 7 1 e3h icu interrupt request destination setting register 227 iselr 227 8 8 2 iclk 0008 7 1 e4h icu interrupt request destination setting register 228 iselr228 8 8 2 iclk 0008 71 e7h icu interrupt request destination setting register 231 iselr231 8 8 2 iclk 0008 7 1 e8h icu interrupt request destination setting register 232 iselr232 8 8 2 iclk 0008 71 ebh icu interrupt request destination setting register 235 iselr235 8 8 2 iclk 0008 7 1 ech icu interrupt request destination setting register 236 iselr236 8 8 2 iclk 0008 71 efh icu interrupt request destination setting register 239 iselr239 8 8 2 iclk 0008 7 1 f0h icu interrupt request destination setting register 240 iselr240 8 8 2 iclk 0008 71f7h icu interrupt request destination setting register 24 7 iselr24 7 8 8 2 iclk 0008 7 1 f8h icu interrupt request destination setting reg ister 248 iselr248 8 8 2 iclk 0008 71fbh icu interrupt request destination setting register 251 iselr 251 8 8 2 iclk 0008 7 1 fch icu interrupt request destination setting register 252 iselr252 8 8 2 iclk 0008 71fdh icu interrupt request destination settin g register 253 iselr253 8 8 2iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 7209h icu interrupt request enable register 09 ier09 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7212h icu interrupt request enable register 12 ier12 8 8 2 iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2 iclk 0008 7214h icu interrupt request enable register 14 ier14 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier 15 8 8 2 iclk 0008 7216 h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier 19 8 8 2 iclk 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 7 3 00h icu interrupt priority register 00 ipr00 8 8 2 iclk 0008 73 01h ic u interrupt priority register 01 ipr01 8 8 2 iclk 0008 7 3 02h icu interrupt priority register 02 ipr02 8 8 2 iclk 0008 73 04h icu interrupt priority register 04 ipr04 8 8 2 iclk 0008 7 3 05h icu interrupt priority register 05 ipr05 8 8 2 iclk 0008 73 06h ic u interrupt priority register 06 ipr06 8 8 2 iclk 0008 7 3 07h icu interrupt priority register 07 ipr07 8 8 2 iclk 0008 73 20h icu interrupt priority register 20 ipr20 8 8 2 iclk
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 43 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 7 3 21h icu interrupt priority register 21 ipr21 8 8 2 iclk 0008 73 22h ic u interrupt priority register 22 ipr22 8 8 2 iclk 0008 7 3 23h icu interrupt priority register 23 ipr23 8 8 2 iclk 0008 73 24h icu interrupt priority register 24 ipr24 8 8 2 iclk 0008 7 3 25h icu interrupt priority register 25 ipr25 8 8 2 iclk 0008 73 26h ic u interrupt priority register 26 ipr26 8 8 2 iclk 0008 7 3 27h icu interrupt priority register 27 ipr27 8 8 2 iclk 0008 7 3 28h icu interrupt priority register 28 ipr28 8 8 2 iclk 0008 7 3 29h icu interrupt priority register 29 ipr29 8 8 2 iclk 0008 73 2ah ic u interrupt priority register 2a ipr2a 8 8 2 iclk 0008 7 3 2bh icu interrupt priority register 2b ipr2b 8 8 2 iclk 0008 73 2ch icu interrupt priority register 2c ipr2c 8 8 2 iclk 0008 7 3 2dh icu interrupt priority register 2d ipr2d 8 8 2 iclk 0008 7 3 2eh ic u interrupt priority register 2e ipr2e 8 8 2 iclk 0008 7 3 2fh icu interrupt priority register 2f ipr2f 8 8 2 iclk 0008 73 40h icu interrupt priority register 40 ipr40 8 8 2 iclk 0008 7 3 44h icu interrupt priority register 44 ipr44 8 8 2 iclk 0008 73 45h ic u interrupt priority register 45 ipr45 8 8 2 iclk 0008 7 3 46h icu interrupt priority register 46 ipr46 8 8 2 iclk 0008 73 47h icu interrupt priority register 47 ipr47 8 8 2 iclk 0008 7 3 4ch icu interrupt priority register 4c ipr4c 8 8 2 iclk 0008 73 4dh ic u interrupt priority register 4d ipr4d 8 8 2 iclk 0008 7 3 4eh icu interrupt priority register 4e ipr4e 8 8 2 iclk 0008 73 4fh icu interrupt priority register 4f ipr4f 8 8 2 iclk 0008 7 3 50h icu interrupt priority register 50 ipr50 8 8 2 iclk 0008 7 3 51h ic u interrupt priority register 51 ipr51 8 8 2 iclk 0008 7 3 52h icu interrupt priority register 52 ipr52 8 8 2 iclk 0008 73 53h icu interrupt priority register 53 ipr53 8 8 2 iclk 0008 7 3 54h icu interrupt priority register 54 ipr54 8 8 2 iclk 0008 73 55h ic u interrupt priority register 55 ipr55 8 8 2 iclk 0008 7 3 56h icu interrupt priority register 56 ipr56 8 8 2 iclk 0008 7 3 57h icu interrupt priority register 57 ipr57 8 8 2 iclk 0008 7 3 58h icu interrupt priority register 58 ipr58 8 8 2 iclk 0008 73 59h ic u interrupt priority register 59 ipr59 8 8 2 iclk 0008 7 3 5ah icu interrupt priority register 5a ipr5a 8 8 2 iclk 0008 73 5bh icu interrupt priority register 5b ipr5b 8 8 2 iclk 0008 7 3 5ch icu interrupt priority register 5c ipr5c 8 8 2 iclk 0008 73 5dh ic u interrupt priority register 5d ipr5d 8 8 2 iclk 0008 7 3 5eh icu interrupt priority register 5e ipr5e 8 8 2 iclk 0008 73 5fh icu interrupt priority register 5f ipr5f 8 8 2 iclk 0008 7 3 60h icu interrupt priority register 60 ipr60 8 8 2 iclk 0008 73 61h ic u interrupt priority register 61 ipr61 8 8 2 iclk 0008 7 3 62h icu interrupt priority register 62 ipr62 8 8 2 iclk 0008 7 3 63h icu interrupt priority register 63 ipr63 8 8 2 iclk 0008 7 3 68h icu interrupt priority register 68 ipr68 8 8 2 iclk
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 44 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 7 3 69h ic u interrupt priority register 69 ipr69 8 8 2 iclk 0008 73 6ah icu interrupt priority register 6a ipr6a 8 8 2 iclk 0008 7 3 6bh icu interrupt priority register 6b ipr6b 8 8 2 iclk 0008 73 70h icu interrupt priority register 70 ipr70 8 8 2 iclk 0008 7 3 71h ic u interrupt priority register 71 ipr71 8 8 2 iclk 0008 73 72h icu interrupt priority register 72 ipr72 8 8 2 iclk 0008 7 3 73h icu interrupt priority register 73 ipr73 8 8 2 iclk 0008 7 3 80h icu interrupt priority register 80 ipr80 8 8 2 iclk 0008 7 3 81h ic u interrupt priority register 81 ipr81 8 8 2 iclk 0008 73 82h icu interrupt priority register 82 ipr82 8 8 2 iclk 0008 7 3 83h icu interrupt priority register 83 ipr83 8 8 2 iclk 0008 73 84h icu interrupt priority register 84 ipr84 8 8 2 iclk 0008 7 3 85h ic u interrupt priority register 85 ipr85 8 8 2 iclk 0008 7 3 86h icu interrupt priority register 86 ipr86 8 8 2 iclk 0008 7388 h icu interrupt priority register 8 8 ipr 88 8 8 2 iclk 0008 73 89h icu interrupt priority register 89 ipr89 8 8 2 iclk 0008 7 3 8ah ic u interrupt priority register 8a ipr8a 8 8 2 iclk 0008 73 8bh icu interrupt priority register 8b ipr8b 8 8 2 iclk 0008 7 3 8 c h icu interrupt priority register 8 c ipr 8c 8 8 2 iclk 0008 73 8dh icu interrupt priority register 8d ipr8d 8 8 2 iclk 0008 7 3 8eh ic u interrupt priority register 8e ipr8e 8 8 2 iclk 0008 73 8fh icu interrupt priority register 8f ipr8f 8 8 2 iclk 0008 7 3f0 h icu fast interrupt register fir 16 16 2 iclk 0008 7 4 00h dtc dtc control register dtccr 8 8 2 iclk 0008 7 4 04h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 7 4 08h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 7 4 0ch dtc dtc module start register dtcst 8 8 2 iclk 0008 8000h cmt (unit 0) compare match timer start register 0 cmstr0 16 16 2 to 3 pclk * 7 0008 8002h cmt 0 compare match timer control register cmcr 16 16 2 to 3 pclk * 7 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2 to 3 pclk * 7 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2 to 3 pclk * 7 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 to 3 pclk * 7 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2 to 3 pclk * 7 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2 to 3 pclk * 7 0008 8010h cmt (unit 1) compare match timer start register 1 cmstr1 16 16 2 to 3 pclk * 7 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 to 3 pclk * 7 0008 8014h cmt2 compare match timer counter cmcnt 16 16 2 to 3 pclk * 7 0008 8016h cmt2 compare match timer constant register cmcor 16 16 2 to 3 pclk * 7 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 to 3 pclk * 7 0008 801ah cmt3 compare match timer counter cmcnt 16 16 2 to 3 pclk * 7 0008 801ch cmt3 compare match timer constant register cmcor 16 16 2 to 3 pclk * 7 0008 8028h w dt timer control/status register tcsr 8 8 2 to 3 pclk * 7 0008 8028h wdt write window a register wina 16 16 2 to 3 pclk * 7 0008 8029h wdt timer counter tcnt 8 8 2 to 3 pclk * 7 0008 802ah wdt write window b register winb 16 16 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 45 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 802bh w dt reset control/status register rstcsr 8 8 2 to 3 pclk * 7 0008 8040h ad0 a/d data register a addra 16 16 2 to 3 pclk * 7 0008 8042h ad0 a/d data register b addrb 16 16 2 to 3 pclk * 7 0008 8044h ad0 a/d data register c addrc 16 16 2 to 3 pclk * 7 0008 80 46h ad0 a/d data register d addrd 16 16 2 to 3 pclk * 7 0008 8050h ad0 a/d control/status register adcsr 8 8 2 to 3 pclk * 7 0008 8051h ad0 a/d control register adcr 8 8 2 to 3 pclk * 7 0008 8052h ad0 addry format select register addpr 8 8 2 to 3 pclk * 7 0008 8053h ad0 a/d sampling state register adsstr 8 8 2 to 3 pclk * 7 0008 8060h ad1 a/d data register a addra 16 16 2 to 3 pclk * 7 0008 8062h ad1 a/d data register b addrb 16 16 2 to 3 pclk * 7 0008 8064h ad1 a/d data register c addrc 16 16 2 to 3 pclk * 7 0008 8066h ad1 a/d data register d addrd 16 16 2 to 3 pclk * 7 0008 8070h ad1 a/d control/status register adcsr 8 8 2 to 3 pclk * 7 0008 8071h ad1 a/d control register adcr 8 8 2 to 3 pclk * 7 0008 8072h ad1 addry format select register addpr 8 8 2 to 3 pclk * 7 0008 8073h ad1 a/d sampling state register adsstr 8 8 2 to 3 pclk * 7 0008 8080h ad2 a/d data register a addra 16 16 2 to 3 pclk * 7 0008 8082h ad2 a/d data register b addrb 16 16 2 to 3 pclk * 7 0008 8084h ad2 a/d data register c addrc 16 16 2 t o 3 pclk * 7 0008 8086h ad2 a/d data register d addrd 16 16 2 to 3 pclk * 7 0008 8090h ad2 a/d control/status register adcsr 8 8 2 to 3 pclk * 7 0008 8091h ad2 a/d control register adcr 8 8 2 to 3 pclk * 7 0008 8092h ad2 addry format select register addpr 8 8 2 to 3 pclk * 7 0008 8093h ad2 a/d sampling state register adsstr 8 8 2 to 3 pclk * 7 0008 80a0h ad3 a/d data register a addra 16 16 2 to 3 pclk * 7 0008 80a2h ad3 a/d data register b addrb 16 16 2 to 3 pclk * 7 0008 80a4h ad3 a/d data register c addrc 16 16 2 to 3 pclk * 7 0008 80a6h ad3 a/d data register d addrd 16 16 2 to 3 pclk * 7 0008 80b0h ad3 a/d control/status register adcsr 8 8 2 to 3 pclk * 7 0008 80b1h ad3 a/d control register adcr 8 8 2 to 3 pclk * 7 0008 80b2h ad3 addry format select regis ter addpr 8 8 2 to 3 pclk * 7 0008 80b3h ad3 a/d sampling state register adsstr 8 8 2 to 3 pclk * 7 0008 80c0h d/a d/a data register 0 dadr0 16 16 2 to 3 pclk * 7 0008 80c2h d/a d/a data register 1 dadr1 16 16 2 to 3 pclk * 7 0008 80c4h d/a d/a control reg ister dacr 8 8 2 to 3 pclk * 7 0008 80c5h d/a dadry format select register dadpr 8 8 2 to 3 pclk * 7 0008 8100h tpu (unit 0) timer start register tstra 8 8 2 to 3 pclk * 7 0008 8101h tpu (unit 0 ) timer synchronous register tsyra 8 8 2 to 3 pclk * 7 0008 81 10h tpu0 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8111h tpu0 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8112h tpu0 timer i/o control register h tiorh 8 8 2 to 3 pclk * 7 0008 8113h tpu0 timer i/o control register l tiorl 8 8 2 to 3 pclk * 7 0008 8114h tpu0 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8115h tpu0 timer status register tsr 8 8 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 46 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 8116h tpu0 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8118h tpu0 timer general register a tgra 16 16 2 to 3 pc lk * 7 0008 811ah tpu0 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 811ch tpu0 timer general register c tgrc 16 16 2 to 3 pclk * 7 0008 811eh tpu0 timer general register d tgrd 16 16 2 to 3 pclk * 7 0008 8120h tpu1 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8121h tpu1 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8122h tpu1 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 8124h tpu1 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8125h tpu1 timer status registe r tsr 8 8 2 to 3 pclk * 7 0008 8126h tpu1 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8128h tpu1 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 812ah tpu1 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 8130h tpu2 timer control registe r tcr 8 8 2 to 3 pclk * 7 0008 8131h tpu2 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8132h tpu2 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 8134h tpu2 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8135h tpu2 timer status register tsr 8 8 2 to 3 pclk * 7 0008 8136h tpu2 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8138h tpu2 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 813ah tpu2 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 8140h tpu3 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8141h tpu3 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8142h tpu3 timer i/o control register h tiorh 8 8 2 to 3 pclk * 7 0008 8143h tpu3 timer i/o control register l tiorl 8 8 2 to 3 pclk * 7 0008 8144h tpu3 tim er interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8145h tpu3 timer status register tsr 8 8 2 to 3 pclk * 7 0008 8146h tpu3 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8148h tpu3 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 814ah tpu3 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 814ch tpu3 timer general register c tgrc 16 16 2 to 3 pclk * 7 0008 814eh tpu3 timer general register d tgrd 16 16 2 to 3 pclk * 7 0008 8150h tpu4 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8151h tpu4 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8152h tpu4 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 8154h tpu4 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8155h tpu4 timer status register tsr 8 8 2 to 3 pclk * 7 0008 8156h tpu4 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8158h tpu4 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 815ah tpu4 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 8160h tpu5 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8161h tpu5 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8162h tpu5 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 8164h tpu5 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8165h tpu5 timer status register tsr 8 8 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 47 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 8166h tpu5 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8168h tpu5 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 816ah tpu5 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 8170h tpu (unit 1) timer start register tstrb 8 8 2 to 3 pclk * 7 0008 8171h tpu (unit 1 ) timer synchronous register tsyrb 8 8 2 to 3 pclk * 7 0008 8180h tpu6 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8181h tpu6 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8182h tpu6 timer i/o control r egister h tiorh 8 8 2 to 3 pclk * 7 0008 8183h tpu6 timer i/o control register l tiorl 8 8 2 to 3 pclk * 7 0008 8184h tpu6 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8185h tpu6 timer status register tsr 8 8 2 to 3 pclk * 7 0008 8186h tpu 6 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8188h tpu6 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 818ah tpu6 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 818ch tpu6 timer general register c tgrc 16 16 2 to 3 pclk * 7 0008 818e h tpu6 timer general register d tgrd 16 16 2 to 3 pclk * 7 0008 8190h tpu7 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8191h tpu7 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 8192h tpu7 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 8194h tpu7 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 8195h tpu7 timer status register tsr 8 8 2 to 3 pclk * 7 0008 8196h tpu7 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 8198h tpu7 timer general register a tgra 16 16 2 to 3 pclk * 7 0 008 819ah tpu7 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 81a0h tpu8 timer control register tcr 8 8 2 to 3 pclk * 7 0008 81a1h tpu8 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 81a2h tpu8 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 81a4h tpu8 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 81a5h tpu8 timer status register tsr 8 8 2 to 3 pclk * 7 0008 81a6h tpu8 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 81a8h tpu8 timer general register a tgra 16 16 2 to 3 pc lk * 7 0008 81aah tpu8 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 81b0h tpu9 timer control register tcr 8 8 2 to 3 pclk * 7 0008 81b1h tpu9 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 81b2h tpu9 timer i/o control register h tiorh 8 8 2 to 3 pclk * 7 0008 81b3h tpu9 timer i/o control register l tiorl 8 8 2 to 3 pclk * 7 0008 81b4h tpu9 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 81b5h tpu9 timer status register tsr 8 8 2 to 3 pclk * 7 0008 81b6h tpu9 timer counter tcnt 1 6 16 2 to 3 pclk * 7 0008 81b8h tpu9 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 81bah tpu9 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 81bch tpu9 timer general register c tgrc 16 16 2 to 3 pclk * 7 0008 81beh tpu9 timer general r egister d tgrd 16 16 2 to 3 pclk * 7 0008 81c0h tpu10 timer control register tcr 8 8 2 to 3 pclk * 7 0008 81c1h tpu10 timer mode register tmdr 8 8 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 48 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 81c2h tpu10 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 81c4h tpu10 timer i nterrupt enable register tier 8 8 2 to 3 pclk * 7 0008 81c5h tpu10 timer status register tsr 8 8 2 to 3 pclk * 7 0008 81c6h tpu10 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 81c8h tpu10 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 81cah tpu10 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 81d0h tpu11 timer control register tcr 8 8 2 to 3 pclk * 7 0008 81d1h tpu11 timer mode register tmdr 8 8 2 to 3 pclk * 7 0008 81d2h tpu11 timer i/o control register tior 8 8 2 to 3 pclk * 7 0008 81d 4h tpu11 timer interrupt enable register tier 8 8 2 to 3 pclk * 7 0008 81d5h tpu11 timer status register tsr 8 8 2 to 3 pclk * 7 0008 81d6h tpu11 timer counter tcnt 16 16 2 to 3 pclk * 7 0008 81d8h tpu11 timer general register a tgra 16 16 2 to 3 pclk * 7 0008 81dah tpu11 timer general register b tgrb 16 16 2 to 3 pclk * 7 0008 81e6h ppg0 ppg output control register pcr 8 8 2 to 3 pclk * 7 0008 81e7h ppg0 ppg output mode register pmr 8 8 2 to 3 pclk * 7 0008 81e8h ppg0 next data enable register h nderh 8 8 2 to 3 pclk * 7 0008 81e9h ppg0 next data enable register l nderl 8 8 2 to 3 pclk * 7 0008 81eah ppg0 output data register h podrh 8 8 2 to 3 pclk * 7 0008 81ebh ppg0 output data register l podrl 8 8 2 to 3 pclk * 7 0008 81e c h * 1 ppg0 next data register h ndrh 8 8 2 to 3 pclk * 7 0008 81edh * 2 ppg0 next data register l ndrl 8 8 2 to 3 pclk * 7 0008 81eeh * 1 ppg0 next data register h ndrh 8 8 2 to 3 pclk * 7 0008 81efh * 2 ppg0 next data register l ndrl 8 8 2 to 3 pclk * 7 0008 81f0h ppg1 ppg trigger select reg ister ptrslr 8 8 2 to 3 pclk * 7 0008 81f6h ppg1 ppg output control register pcr 8 8 2 to 3 pclk * 7 0008 81f7h ppg1 ppg output mode register pmr 8 8 2 to 3 pclk * 7 0008 81f8h ppg1 next data enable register h nderh 8 8 2 to 3 pclk * 7 0008 81f9h ppg1 next data enable register l nderl 8 8 2 to 3 pclk * 7 0008 81fah ppg1 output data register h podrh 8 8 2 to 3 pclk * 7 0008 81fbh ppg1 output data register l podrl 8 8 2 to 3 pclk * 7 0008 81fch * 3 ppg1 next data register h ndrh 8 8 2 to 3 pclk * 7 0008 81fdh * 4 ppg1 next data register l ndrl 8 8 2 to 3 pclk * 7 0008 81feh * 3 ppg1 next data register h ndrh 8 8 2 to 3 pclk * 7 0008 81ffh * 4 ppg1 next data register l ndrl 8 8 2 to 3 pclk * 7 0008 8200h tmr0 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8201h tm r1 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8202h tmr0 timer control/status register tcsr 8 8 2 to 3 pclk * 7 0008 8203h tmr1 timer control/status register tcsr 8 8 2 to 3 pclk * 7 0008 8204h tmr0 time constant register a tcora 8 8 or 16 2 to 3 pclk * 7 0008 8205h tmr1 time constant register a tcora 8 8 or 16 * 5 2 to 3 pclk * 7 0008 8206h tmr0 time constant register b tcorb 8 8 or 16 2 to 3 pclk * 7 0008 8207h tmr1 time constant register b tcorb 8 8 or 16 * 5 2 to 3 pclk * 7 0008 8208h tmr0 timer co unter tcnt 8 8 or 16 2 to 3 pclk * 7 0008 8209h tmr1 timer counter tcnt 8 8 or 16 * 5 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 49 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 820ah tmr0 timer counter control register tccr 8 8 or 16 2 to 3 pclk * 7 0008 820bh tmr1 timer counter control register tccr 8 8 or 16 2 to 3 pclk * 7 0008 8210h tmr2 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8211h tmr3 timer control register tcr 8 8 2 to 3 pclk * 7 0008 8212h tmr2 timer control/status register tcsr 8 8 2 to 3 pclk * 7 0008 8213h tmr3 timer control/status register tcsr 8 8 2 to 3 pclk * 7 0008 8214h tmr2 time constant register a tcora 8 8 or 16 2 to 3 pclk * 7 0008 8215h tmr3 time constant register a tcora 8 8 or 16 * 5 2 to 3 pclk * 7 0008 8216h tmr2 time constant register b tcorb 8 8 or 16 2 to 3 pclk * 7 0008 8217h tmr3 time co nstant register b tcorb 8 8 or 16 * 5 2 to 3 pclk * 7 0008 8218h tmr2 timer counter tcnt 8 8 or 16 2 to 3 pclk * 7 0008 8219h tmr3 timer counter tcnt 8 8 or 16 * 5 2 to 3 pclk * 7 0008 821ah tmr2 timer counter control register tccr 8 8 or 16 2 to 3 pclk * 7 00 08 821bh tmr3 timer counter control register tccr 8 8 or 16 2 to 3 pclk * 7 0008 8240h sci0 serial mode register smr * 6 8 8 2 to 3 pclk * 7 0008 8241h sci0 bit rate register brr 8 8 2 to 3 pclk * 7 0008 8242h sci0 serial control register scr * 6 8 8 2 to 3 pc lk * 7 0008 8243h sci0 transmit data register tdr 8 8 2 to 3 pclk * 7 0008 8244h sci0 serial status register ssr * 6 8 8 2 to 3 pclk * 7 0008 8245h sci0 receive data register rdr 8 8 2 to 3 pclk * 7 0008 8246h sci0 smart card mode register scmr 8 8 2 to 3 pc lk * 7 0008 8247h sci0 serial extended mode register semr 8 8 2 to 3 pclk * 7 0008 8248h sci1 serial mode register smr * 6 8 8 2 to 3 pclk * 7 0008 8249h sci1 bit rate register brr 8 8 2 to 3 pclk * 7 0008 824ah sci1 serial control register scr * 6 8 8 2 to 3 pclk * 7 0008 824bh sci1 transmit data register tdr 8 8 2 to 3 pclk * 7 0008 824ch sci1 serial status register ssr * 6 8 8 2 to 3 pclk * 7 0008 824dh sci1 receive data register rdr 8 8 2 to 3 pclk * 7 0008 824eh sci1 smart card mode register scmr 8 8 2 to 3 pclk * 7 0008 824fh sci1 serial extended mode register semr 8 8 2 to 3 pclk * 7 0008 8250h sci2 serial mode register smr * 6 8 8 2 to 3 pclk * 7 0008 8251h sci2 bit rate register brr 8 8 2 to 3 pclk * 7 0008 8252h sci2 serial control register scr * 6 8 8 2 to 3 pclk * 7 0008 8253h sci2 transmit data register tdr 8 8 2 to 3 pclk * 7 0008 8254h sci2 serial status register ssr * 6 8 8 2 to 3 pclk * 7 0008 8255h sci2 receive data register rdr 8 8 2 to 3 pclk * 7 0008 8256h sci2 smart card mode register scmr 8 8 2 to 3 pclk * 7 0008 8257h sci2 serial extended mode register semr 8 8 2 to 3 pclk * 7 0008 8258h sci3 serial mode register smr * 6 8 8 2 to 3 pclk * 7 0008 8259h sci3 bit rate register brr 8 8 2 to 3 pclk * 7 0008 825ah sci3 serial control register scr * 6 8 8 2 t o 3 pclk * 7 0008 825bh sci3 transmit data register tdr 8 8 2 to 3 pclk * 7 0008 825ch sci3 serial status register ssr * 6 8 8 2 to 3 pclk * 7 0008 825dh sci3 receive data register rdr 8 8 2 to 3 pclk * 7 0008 825eh sci3 smart card mode register scmr 8 8 2 t o 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 50 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 825fh sci3 serial extended mode register semr 8 8 2 to 3 pclk * 7 0008 8260h sci4 serial mode register smr * 6 8 8 2 to 3 pclk * 7 0008 8261h sci4 bit rate register brr 8 8 2 to 3 pclk * 7 0008 8262h sci4 serial control register scr * 6 8 8 2 to 3 pclk * 7 0008 8263h sci4 transmit data register tdr 8 8 2 to 3 pclk * 7 0008 8264h sci4 serial status register ssr * 6 8 8 2 to 3 pclk * 7 0008 8265h sci4 receive data register rdr 8 8 2 to 3 pclk * 7 0008 8266h sci4 smart card mode register scmr 8 8 2 to 3 pclk * 7 0008 8267h sci4 serial extended mode register semr 8 8 2 to 3 pclk * 7 0008 8268h sci5 serial mode register smr * 6 8 8 2 to 3 pclk * 7 0008 8269h sci5 bit rate register brr 8 8 2 to 3 pclk * 7 0008 826ah sci5 serial control register scr * 6 8 8 2 to 3 pclk * 7 0008 826bh sci5 transmit data register tdr 8 8 2 to 3 pclk * 7 0008 826ch sci5 serial status register ssr * 6 8 8 2 to 3 pclk * 7 0008 826dh sci5 receive data register rdr 8 8 2 to 3 pclk * 7 0008 826eh sci5 smart card mode register scmr 8 8 2 to 3 pclk * 7 0008 826fh sci5 serial extended mode register semr 8 8 2 to 3 pclk * 7 0008 8270h sci6 serial mode register smr * 6 8 8 2 to 3 pclk * 7 0008 8271h sci6 bit rate register brr 8 8 2 to 3 pclk * 7 0008 8272h sci6 serial control register scr * 6 8 8 2 to 3 pclk * 7 0008 8273h sci6 transmit data register tdr 8 8 2 to 3 pclk * 7 0008 8274h sci6 serial status register ssr * 6 8 8 2 to 3 pclk * 7 0008 8275h sci6 receive data register rdr 8 8 2 to 3 pclk * 7 0008 8276h sci6 smart card mode register scmr 8 8 2 to 3 pclk * 7 0008 8277h sci6 serial extended mode register semr 8 8 2 to 3 pclk * 7 0008 8280h crc crc control register crccr 8 8 2 to 3 pclk * 7 0008 8281h crc crc data input register crcdir 8 8 2 to 3 pclk * 7 0008 8282h crc crc data output registe r crcdor 16 16 2 to 3 pclk * 7 0008 8300h r iic0 i 2 c bus control register 1 iccr1 8 8 2 to 3 pclk * 7 0008 8301h r iic0 i 2 c bus control register 2 iccr2 8 8 2 to 3 pclk * 7 0008 8302h r iic0 i 2 c bus mode register 1 icmr1 8 8 2 to 3 pclk * 7 0008 8303h r iic0 i 2 c bus mode register 2 icmr2 8 8 2 to 3 pclk * 7 0008 8304h r iic0 i 2 c bus mode register 3 icmr3 8 8 2 to 3 pclk * 7 0008 8305h r iic0 i 2 c bus function enable register icfer 8 8 2 to 3 pclk * 7 0008 8306h r iic0 i 2 c bus status enable register icser 8 8 2 to 3 pclk * 7 0008 8307h r iic0 i 2 c bus interrupt enable register icier 8 8 2 to 3 pclk * 7 0008 8308h r iic0 i 2 c bus status register 1 icsr1 8 8 2 to 3 pclk * 7 0008 8309h r iic0 i 2 c bus status register 2 icsr2 8 8 2 to 3 pclk * 7 0008 830ah r iic0 slave address register l 0 sar l 0 8 8 2 to 3 pclk * 7 0008 830ah riic0 internal control for timeout l tmocntl 16 16 2 to 3 pclk * 7 0008 830bh r iic0 slave address register u 0 sar u 0 8 8 2 to 3 pclk * 7 0008 830bh riic0 internal control for timeout u tmocntu 16 16 2 to 3 pc lk * 7 0008 830ch r iic0 slave address register l 1 sar l 1 8 8 2 to 3 pclk * 7 0008 830dh r iic0 slave address register u 1 sar u 1 8 8 2 to 3 pclk * 7 0008 830eh r iic0 slave address register l 2 sar l 2 8 8 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 51 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 830fh r iic0 slave address register u 2 sar u 2 8 8 2 to 3 pclk * 7 0008 8310h r iic0 i 2 c bus bit rate low - level register icbrl 8 8 2 to 3 pclk * 7 0008 8311h r iic0 i 2 c bus bit rate high - level register icbrh 8 8 2 to 3 pclk * 7 0008 8312h r iic0 i 2 c bus transmit data register icdrt 8 8 2 to 3 pclk * 7 0008 8313h r iic0 i 2 c bus receive data register icdrr 8 8 2 to 3 pclk * 7 0008 8320h r iic 1 i 2 c bus control register 1 iccr1 8 8 2 to 3 pclk * 7 0008 8321h r iic 1 i 2 c bus control register 2 iccr2 8 8 2 to 3 pclk * 7 0008 8322h r iic 1 i 2 c bus mode register 1 icmr1 8 8 2 to 3 pclk * 7 0008 8323h r iic 1 i 2 c bus mode register 2 icmr2 8 8 2 to 3 pclk * 7 0008 8324h r iic 1 i 2 c bus mode register 3 icmr3 8 8 2 to 3 pclk * 7 0008 8325h r iic 1 i 2 c bus function enable register icfer 8 8 2 to 3 pclk * 7 0008 8326h r iic 1 i 2 c bus status enable register icser 8 8 2 to 3 pclk * 7 0008 8327h r iic 1 i 2 c bus interrupt enable register icier 8 8 2 to 3 pclk * 7 0008 8328h r iic 1 i 2 c bus status register 1 icsr1 8 8 2 to 3 pclk * 7 0008 8329h r iic 1 i 2 c bus status register 2 icsr2 8 8 2 to 3 pclk * 7 0008 832ah r iic 1 slave address register l 0 sar l0 8 8 2 to 3 pclk * 7 0008 832ah riic1 internal control for timeout l tmocntl 16 16 2 to 3 pclk * 7 0008 832bh r iic 1 slave address register u 0 sar u0 8 8 2 to 3 pclk * 7 0008 832bh riic1 internal control for timeout u tmocntu 16 16 2 to 3 pclk * 7 0008 832ch r iic 1 slave address register l 1 sar l1 8 8 2 to 3 pclk * 7 0008 832dh r iic 1 slave address register u 1 sar u 1 8 8 2 to 3 pclk * 7 0008 832eh r iic 1 slave address register l 2 sar l2 8 8 2 to 3 pclk * 7 0008 832fh r iic 1 slave address register u 2 sar u 2 8 8 2 to 3 pclk * 7 0008 8330h r iic 1 i 2 c bus bit rate low - level register icbrl 8 8 2 to 3 pclk * 7 0008 8331h r iic 1 i 2 c bus bit rate high - level register icbrh 8 8 2 to 3 pclk * 7 0008 8332h r iic 1 i 2 c bus transmit data register icdrt 8 8 2 to 3 pclk * 7 0008 8333h r iic 1 i 2 c bus receive data register icdrr 8 8 2 to 3 pclk * 7 0008 c000h p0 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c001h p1 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c002 h p2 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c003h p3 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c004h p4 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c005h p5 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c006h p6 dat a direction register ddr 8 8 2 to 3 pclk * 7 0008 c007h p7 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c008h p8 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c009h p9 data direction register ddr 8 8 2 to 3 pclk * 7 0008 c00ah pa data direction register ddr 8 8 2 to 3 pclk * 7 0008 c00bh pb data direction register ddr 8 8 2 to 3 pclk * 7 0008 c00ch pc data direction register ddr 8 8 2 to 3 pclk * 7 0008 c00dh pd data direction register ddr 8 8 2 to 3 pclk * 7 0008 c00eh pe data direction regi ster ddr 8 8 2 to 3 pclk * 7 0008 c00fh pf data direction register ddr 8 8 2 to 3 pclk * 7 0008 c010h pg data direction register ddr 8 8 2 to 3 pclk * 7 0008 c011h ph data direction register ddr 8 8 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 52 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 c020h p0 data register dr 8 8 2 to 3 pclk * 7 0008 c021h p1 data register dr 8 8 2 to 3 pclk * 7 0008 c022h p2 data register dr 8 8 2 to 3 pclk * 7 0008 c023h p3 data register dr 8 8 2 to 3 pclk * 7 0008 c024h p4 data register dr 8 8 2 to 3 pclk * 7 0008 c025h p5 data register dr 8 8 2 to 3 pclk * 7 0008 c026h p6 data register dr 8 8 2 to 3 pclk * 7 0008 c027h p7 data register dr 8 8 2 to 3 pclk * 7 0008 c028h p8 data register dr 8 8 2 to 3 pclk * 7 0008 c029h p9 data register dr 8 8 2 to 3 pclk * 7 0008 c02ah pa data register dr 8 8 2 to 3 p clk * 7 0008 c02bh pb data register dr 8 8 2 to 3 pclk * 7 0008 c02ch pc data register dr 8 8 2 to 3 pclk * 7 0008 c02dh pd data register dr 8 8 2 to 3 pclk * 7 0008 c02eh pe data register dr 8 8 2 to 3 pclk * 7 0008 c02fh pf data register dr 8 8 2 to 3 pc lk * 7 0008 c030h pg data register dr 8 8 2 to 3 pclk * 7 0008 c031h ph data register dr 8 8 2 to 3 pclk * 7 0008 c040h p0 port register port 8 8 2 to 3 pclk * 7 0008 c041h p1 port register port 8 8 2 to 3 pclk * 7 0008 c042h p2 port register port 8 8 2 to 3 pclk * 7 0008 c043h p3 port register port 8 8 2 to 3 pclk * 7 0008 c044h p4 port register port 8 8 2 to 3 pclk * 7 0008 c045h p5 port register port 8 8 2 to 3 pclk * 7 0008 c046h p6 port register port 8 8 2 to 3 pclk * 7 0008 c047h p7 port register port 8 8 2 to 3 pclk * 7 0008 c048h p8 port register port 8 8 2 to 3 pclk * 7 0008 c049h p9 port register port 8 8 2 to 3 pclk * 7 0008 c04ah pa port register port 8 8 2 to 3 pclk * 7 0008 c04bh pb port register port 8 8 2 to 3 pclk * 7 0008 c04ch pc port regi ster port 8 8 2 to 3 pclk * 7 0008 c04dh pd port register port 8 8 2 to 3 pclk * 7 0008 c04eh pe port register port 8 8 2 to 3 pclk * 7 0008 c04fh pf port register port 8 8 2 to 3 pclk * 7 0008 c050h pg port register port 8 8 2 to 3 pclk * 7 0008 c051h ph port register port 8 8 2 to 3 pclk * 7 0008 c060h p0 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c061h p1 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c062h p2 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c063h p3 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c064h p4 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c065h p5 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c066h p6 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c067h p7 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c068h p8 input buffer control register icr 8 8 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 53 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 c069h p9 input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c06ah pa input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c06bh pb input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c06ch pc input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c06dh pd input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c06eh pe input buffer contro l register icr 8 8 2 to 3 pclk * 7 0008 c06fh pf input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c070h pg input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c071h ph input buffer control register icr 8 8 2 to 3 pclk * 7 0008 c082h p2 ope n drain control register odr 8 8 2 to 3 pclk * 7 0008 c08ch pc open drain control register odr 8 8 2 to 3 pclk * 7 0008 c0cah pa pull - up resistor control register pcr 8 8 2 to 3 pclk * 7 0008 c0cbh pb pull - up resistor control register pcr 8 8 2 to 3 pclk * 7 0008 c0cch pc pull - up resistor control register pcr 8 8 2 to 3 pclk * 7 0008 c0cdh pd pull - up resistor control register pcr 8 8 2 to 3 pclk * 7 0008 c0ceh pe pull - up resistor control register pcr 8 8 2 to 3 pclk * 7 0008 c100h i/o port port function con trol register 0 pfcr0 8 8 2 to 3 pclk * 7 0008 c101h i/o port port function control register 1 pfcr1 8 8 2 to 3 pclk * 7 0008 c102h i/o port port function control register 2 pfcr2 8 8 2 to 3 pclk * 7 0008 c103h i/o port port function control register 3 pfc r3 8 8 2 to 3 pclk * 7 0008 c104h i/o port port function control register 4 pfcr4 8 8 2 to 3 pclk * 7 0008 c105h i/o port port function control register 5 pfcr5 8 8 2 to 3 pclk * 7 0008 c106h i/o port port function control register 6 pfcr6 8 8 2 to 3 pclk * 7 0008 c107h i/o port port function control register 7 pfcr7 8 8 2 to 3 pclk * 7 0008 c108h i/o port port function control register 8 pfcr8 8 8 2 to 3 pclk * 7 0008 c109h i/o port port function control register 9 pfcr9 8 8 2 to 3 pclk * 7 0008 c280h syst em deep standby control register dpsbycr 8 8 4 to 5 pclk * 7 0008 c281h system deep standby wait control register dpswcr 8 8 4 to 5 pclk * 7 0008 c282h system deep standby interrupt enable register dpsier 8 8 4 to 5 pclk * 7 0008 c283h system deep standby interrupt flag register dpsifr 8 8 4 to 5 pclk * 7 0008 c284h system deep standby interrupt edge register dpsiegr 8 8 4 to 5 pclk * 7 0008 c285h system reset status register rstsr 8 8 4 to 5 pclk * 7 0008 c289h flash flash write erase protection register f wepror 8 8 4 to 5 pclk * 7 0008 c290h system deep standby backup register 0 dpsbkr0 8 8 4 to 5 pclk * 7 0008 c291h system deep standby backup register 1 dpsbkr1 8 8 4 to 5 pclk * 7 0008 c292h system deep standby backup register 2 dpsbkr2 8 8 4 to 5 pclk * 7 0008 c293h system deep standby backup register 3 dpsbkr3 8 8 4 to 5 pclk * 7 0008 c294h system deep standby backup register 4 dpsbkr4 8 8 4 to 5 pclk * 7 0008 c295h system deep standby backup register 5 dpsbkr5 8 8 4 to 5 pclk * 7 0008 c296h system deep standby backup register 6 dpsbkr6 8 8 4 to 5 pclk * 7 0008 c297h system deep standby backup register 7 dpsbkr7 8 8 4 to 5 pclk * 7 0008 c298h system deep standby backup register 8 dpsbkr8 8 8 4 to 5 pclk * 7 0008 c299h system deep standby backup register 9 dpsbkr9 8 8 4 to 5 pclk * 7 0008 c29ah system deep standby backup register 10 dpsbkr10 8 8 4 to 5 pclk * 7 0008 c29bh system deep standby backup register 11 dpsbkr11 8 8 4 to 5 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 54 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 c29ch system deep standby backup register 12 dpsbkr12 8 8 4 to 5 pclk * 7 0008 c29dh system deep standby backup register 13 dpsbkr13 8 8 4 to 5 pclk * 7 0008 c29eh system deep standby backup register 14 dpsbkr14 8 8 4 to 5 pclk * 7 0008 c29fh system deep standby backup register 15 dpsbkr15 8 8 4 to 5 pclk * 7 0008 c2a0 h system deep standby backup register 16 dpsbkr16 8 8 4 to 5 pclk * 7 0008 c2a1h system deep standby backup register 17 dpsbkr17 8 8 4 to 5 pclk * 7 0008 c2a2h system deep standby backup register 18 dpsbkr18 8 8 4 to 5 pclk * 7 0008 c2a3h system deep stand by backup register 19 dpsbkr19 8 8 4 to 5 pclk * 7 0008 c2a4h system deep standby backup register 20 dpsbkr20 8 8 4 to 5 pclk * 7 0008 c2a5h system deep standby backup register 21 dpsbkr21 8 8 4 to 5 pclk * 7 0008 c2a6h system deep standby backup register 22 dpsbkr22 8 8 4 to 5 pclk * 7 0008 c2a7h system deep standby backup register 23 dpsbkr23 8 8 4 to 5 pclk * 7 0008 c2a8h system deep standby backup register 24 dpsbkr24 8 8 4 to 5 pclk * 7 0008 c2a9h system deep standby backup register 25 dpsbkr25 8 8 4 t o 5 pclk * 7 0008 c2aah system deep standby backup register 26 dpsbkr26 8 8 4 to 5 pclk * 7 0008 c2abh system deep standby backup register 27 dpsbkr27 8 8 4 to 5 pclk * 7 0008 c2ach system deep standby backup register 28 dpsbkr28 8 8 4 to 5 pclk * 7 0008 c 2adh system deep standby backup register 29 dpsbkr29 8 8 4 to 5 pclk * 7 0008 c2aeh system deep standby backup register 30 dpsbkr30 8 8 4 to 5 pclk * 7 0008 c2afh system deep standby backup register 31 dpsbkr31 8 8 4 to 5 pclk * 7 0008 c300h icu irq detect ion enable registrar 0 irqer0 8 8 2 to 3 pclk * 7 0008 c301h icu irq detection enable registrar 1 irqer1 8 8 2 to 3 pclk * 7 0008 c302h icu irq detection enable registrar 2 irqer2 8 8 2 to 3 pclk * 7 0008 c303h icu irq detection enable registrar 3 irqer3 8 8 2 to 3 pclk * 7 0008 c304h icu irq detection enable registrar 4 irqer4 8 8 2 to 3 pclk * 7 0008 c305h icu irq detection enable registrar 5 irqer5 8 8 2 to 3 pclk * 7 0008 c306h icu irq detection enable registrar 6 irqer6 8 8 2 to 3 pclk * 7 0008 c307h i cu irq detection enable registrar 7 irqer7 8 8 2 to 3 pclk * 7 0008 c308h icu irq detection enable registrar 8 irqer8 8 8 2 to 3 pclk *7 0008 c309h icu irq detection enable registrar 9 irqer9 8 8 2 to 3 pclk * 7 0008 c30ah icu irq detection enable registr ar 10 irqer10 8 8 2 to 3 pclk * 7 0008 c30bh icu irq detection enable registrar 11 irqer11 8 8 2 to 3 pclk * 7 0008 c30ch icu irq detection enable registrar 12 irqer12 8 8 2 to 3 pclk * 7 0008 c30dh icu irq detection enable registrar 13 irqer13 8 8 2 to 3 pclk * 7 0008 c30eh icu irq detection enable registrar 14 irqer14 8 8 2 to 3 pclk * 7 0008 c30fh icu irq detection enable registrar 15 irqer15 8 8 2 to 3 pclk * 7 0008 c320h icu irq control register 0 irqcr0 8 8 2 to 3 pclk * 7 0008 c321h icu irq control r egister 1 irqcr1 8 8 2 to 3 pclk * 7 0008 c322h icu irq control register 2 irqcr2 8 8 2 to 3 pclk * 7 0008 c323h icu irq control register 3 irqcr3 8 8 2 to 3 pclk * 7 0008 c324h icu irq control register 4 irqcr4 8 8 2 to 3 pclk * 7 0008 c325h icu irq contr ol register 5 irqcr5 8 8 2 to 3 pclk * 7 0008 c326h icu irq control register 6 irqcr6 8 8 2 to 3 pclk * 7 0008 c327h icu irq control register 7 irqcr7 8 8 2 to 3 pclk * 7 0008 c328h icu irq control register 8 irqcr8 8 8 2 to 3 pclk * 7
rx610 group 4 . i/o registers r 01ds0097ej012 0 rev.1. 20 page 55 of 84 feb 20 , 201 3 address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 c329h icu irq c ontrol register 9 irqcr9 8 8 2 to 3 pclk * 7 0008 c32ah icu irq control register 10 irqcr10 8 8 2 to 3 pclk * 7 0008 c32bh icu irq control register 11 irqcr11 8 8 2 to 3 pclk * 7 0008 c32ch icu irq control register 12 irqcr12 8 8 2 to 3 pclk * 7 0008 c32dh icu irq control register 13 irqcr13 8 8 2 to 3 pclk * 7 0008 c32eh icu irq control register 14 irqcr14 8 8 2 to 3 pclk * 7 0008 c32fh icu irq control register 15 irqcr15 8 8 2 to 3 pclk * 7 0008 c340h icu software standby release irq enable register ssier 16 16 2 to 3 pclk * 7 0008 c350h icu non - maskable interrupt enable register nmier 8 8 2 to 3 pclk * 7 0008 c351h icu nmi pin interrupt control register nmicr 8 8 2 to 3 pclk * 7 0008 c352h icu non - maskable interrupt status register nmisr 8 8 2 to 3 pclk * 7 0008 c353h icu non - maskable interrupt clear register nmiclr 8 8 2 to 3 pclk * 7 007f c402h flash flash mode register fmodr 8 8 2 to 3 pclk * 7 007f c410h flash flash access status register fastat 8 8 2 to 3 pclk * 7 007f c411h flash flash access error i nterrupt enable register faeint 8 8 2 to 3 pclk * 7 007f c412h flash flash ready interrupt enable register frdyie 8 8 2 to 3 pclk * 7 007f c440h flash data flash read enable register dflre 16 16 2 to 3 pclk * 7 007f c450h flash data flash programming/erasure enable register dflwe 16 16 2 to 3 pclk * 7 007f c454h flash fcu ram enable register fcurame 16 16 2 to 3 pclk * 7 007f ffb0h flash flash status register 0 fstatr0 8 8 2 to 3 pclk * 7 007f ffb1h flash flash status register 1 fstatr1 8 8 2 to 3 pclk * 7 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 to 3 pclk * 7 007f ffb4h flash flash protection register fprotr 16 16 2 to 3 pclk * 7 007f ffb6h flash flash reset register fresetr 16 16 2 to 3 pclk * 7 007f ffbah flash fcu command register f cmdr 16 16 2 to 3 pclk * 7 007f ffc8h flash fcu processing switching register fcpsr 16 16 2 to 3 pclk * 7 007f ffcah flash data flash blank check control register dflbccnt 16 16 2 to 3 pclk * 7 007f ffcch flash flash p/e status register fpestat 16 16 2 to 3 pclk * 7 007f ffceh flash data flash blank check status register dflbcstat 16 16 2 to 3 pclk * 7 007f ffe8h flash peripheral clock notification register pckar 16 16 2 to 3 pclk * 7 notes: 1. when the same output trigger is specified for pulse output groups 2 and 3 by the ppg0.pcr setting, the ppg0.ndrh address is 000881ech . when different output triggers are specified, the ppg0.ndrh addresses for pulse output groups 2 and 3 are 000881eeh and 000881ech , respectively. 2. when the same output trigger is specified for pulse output groups 0 and 1 by the ppg0.pcr setting, the ppg0.ndrl address is 000881edh . when different output triggers are specified, the ppg0.ndrl addresses for pulse output groups 0 and 1 are 000881efh and 000881edh , respectively. 3. when th e same output trigger is specified for pulse output groups 6 and 7 by the ppg1.pcr setting, the ppg1.ndrh address is 000881fch . when different output triggers are specified, the ppg1.ndrh addresses for pulse output groups 6 and 7 are 000881feh and 000881fc h , respectively. 4. when the same output trigger is specified for pulse output groups 4 and 5 by the ppg1.pcr setting, the ppg1.ndrl address is 000881fdh . when different output triggers are specified, the ppg1.ndrl addresses for pulse output groups 4 and 5 are 000881ffh and 000881fd h, respectively. 5. 16- bit access to odd addresses is prohibited. when 16 - bit access is required, access is at the addre ss corresponding to tmr0 or tmr2 . 6. for certain bits, functions differ according to whether the mode is s erial communication s or smart card interface. 7. the number of access cycles varies depending on the number of divided cycles for clock synchronization (0 to one pclk). 8. the number of access cycles may be 5 iclk if the register is accessed during the dmac operation.
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 56 of 84 f eb 20 , 201 3 5. electrical characteristics 5.1 absolute maximum ratings table 5.1 absolute maximum ratings item symbol value unit power supply voltage v cc , pllv cc - 0.3 to + 4.6 v input voltage (except for ports 0, 14 to 17) v in - 0.3 to v cc + 0.3 v input voltage (ports 0, 14 to 17 * 1 ) v in - 0.3 to +6.5 v reference power supply voltage v refh - 0.3 to v cc + 0.3 v analog power supply voltage av cc * 2 - 0.3 to + 4.6 v analog input voltage v an - 0.3 to v cc + 0.3 v operating temperature t opr regular specificati ons : - 20 to +85 c wide - range specifications : - 40 to + 85 storage temperature t stg - 55 to + 125 c caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. notes: 1. ports 0, and 14 to 17 are 5 v tolerant. 2. c onnect av cc to v cc. when neither the a/d converter nor the d/a converter is in use, do not leave the av ss , v refh , and v refl pins open. connect the av cc and v refh pins to v cc , and the av ss and v refl pins to v ss , respectively.
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 57 of 84 f eb 20 , 201 3 5.2 dc characteristics table 5.2 dc characteristics conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item symbol min . typ . max . un it test conditions schmitt trigger input voltage irq input pin * 1 tpu input pin * 1 tmr input pin * 1 sci input pin * 1 adtrg # input pin * 1 res# , nmi v ih v cc x 0.8 ? v cc + 0.3 v v il - 0.3 ? v cc x 0.2 v t v cc x 0.06 ? ? r iic input pin v ih v cc x 0.7 ? 5.8 v il - 0.3 ? v cc x 0. 3 v t v cc x 0.0 5 ? ? ports 0, 14 to 17 * 2 v ih v cc x 0.8 ? 5.8 v il - 0.3 ? v cc x 0.2 ports 10 to 13, ports 2 to e (144 - pin lqfp) ports 2 to h (176 - pin lfbga) other input pins v ih v cc x 0.8 ? v cc + 0.3 v il - 0.3 ? v cc x 0. 2 input high voltage (except schmitt trigger input pin) md pin, emle v ih v cc x 0.9 ? v cc + 0.3 v extal v cc x 0.8 ? v cc + 0.3 d0 to d15 v cc x 0.7 ? v cc + 0.3 input low voltage (except schmitt trigger input pin) md pin, emle v il - 0.3 ? v cc x 0.1 v extal - 0.3 ? v cc x 0.2 d0 to d15 - 0.3 ? v cc x 0. 3 output high voltage all output pins v oh v cc - 0.5 ? ? v i oh = -1 ma output low voltage all output pins (except for riic pin s) v ol ? ? 0. 5 v i ol = 1. 0 ma riic pins ? ? 0. 4 i ol = 3. 0 ma ? ? 0.6 i ol = 6. 0 ma riic pins (only p14 and p15 in channel 1) ? ? 0.4 i ol = 15 ma (icfer.fmpe = 1 ) ? 0.4 ? i ol = 20 ma (icfer.fmpe = 1 ) input leakage current res# , md pin, e mle, nmi ? i in ? ? ? 1.0 a v in = 0 v, v cc three - state leakage current (off state) ports 10 to 13, ports 2 to e (144 - pin lqfp) ports 2 to h (176 - pin lfbga) ? i tsi ? ? ? 1.0 a v in = 0 v, v cc port 0, ports 14 to 17 ? ? 5.0
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 58 of 84 f eb 20 , 201 3 item symbol min . typ . max . unit test conditions inp ut pull - up resistor current ports a to e -i p 10 ? 300 a v cc = 3.0 to 3.6 v , v in = 0 v input capacitance all input pins (except port 0, ports 14 to 17) c in ? ? 15 pf v in = 0 v , f = 1 mhz , t a = 25 c port 0, ports 14 to 17 ? ? 30 supply current * 3 in operation max. * 4 i cc * 5 ? ? 100 ma iclk = 100 mhz pclk = 50 mhz bclk = 25 mhz normal * 6 ? 35 ? increased by bgo operation * 7 ? 15 ? sleep ? 18 52 all - module - clock - stop mode * 8 ? 14 28 standby mode software standby mode ? 0.08 3.0 deep software standby mode ram retained ? 15 200 a ram power supply halted ? 0.9 26 analog power supply current during a/d con version (per unit) ai cc ? 0.8 1.2 ma during d/a con version (per unit) ? 0.3 1.0 a idle (all units) ? 0.3 1.0 reference power supply current during a/d con ver sion (per unit) ? 0.06 0.1 ma during d/a con version (per unit) ? 0.4 0.6 idle (all units) ? 0.3 1.0 a ram standby voltage v ram 2.5 ? ? v v cc start voltage * 9 v ccstart ? ? 0.8 v v cc rising gradient * 9 sv cc ? ? 20 ms/v notes: 1 . this does n ot include the pins, which are multiplexed as ports 0, and 14 to 17 for 5 v tolerant. 2. this includes the multiplexed pins, but riic input pins for ports 14 to 17 are excluded. 3. supply current values are with all output pins unloaded, all input pins for v ih = v cc and v il = 0 v, and all input pull - up resistors in the off state. 4. measured with clocks supplied to the peripheral functions. this does not include the bgo operation. 5. i cc depends on f (iclk) as follows. (iclk : pclk : bclk = 8 : 4: 2) i cc m ax. = 0.89 x f + 11 ( max. ) i cc typ . = 0.30 x f + 5 ( normal operation ) i cc max. = 0.41 x f + 11 (sleep mode) 6. measured with clocks not supplied to the peripheral functions. this does not include the bgo operation. 7. incremented if data is written to or e rased from the rom or data flash for data storage during the program execution. 8. the values are for reference. 9. this can be applied when the res # pin is held low at power - on.
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 59 of 84 f eb 20 , 201 3 table 5.3 permissible output currents conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item symbol min . typ . max . unit permissible output low current (average value per pin) all output pins except for riic pins i ol ? ? 2.0 ma riic pins (icfer.fmpe = 0) i ol ? ? 6.0 ma riic pins (icfer.fmpe = 1) i ol ? ? 20.0 ma permissible output low current (max. value per pin) all output pins except for riic pins i ol ? ? 4.0 ma riic pins (icfer.fmpe = 0) i ol ? ? 6.0 ma riic pins (icfer.fmpe = 1) i ol ? ? 20.0 ma permissible output low current (total) total of all output pins i ol ? ? 80 ma permissible output high current (average value per pin) all output pins -i oh ? ? 2.0 ma permissible output high current (max. value per pin) all output pins -i oh ? ? 4.0 ma permissible output high current (total) total of all output pins -i oh ? ? 80 ma caution: to protect the lsi's reliability, do not exceed the output current values in table 5 .3.
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 60 of 84 f eb 20 , 201 3 5.3 ac characteristics table 5.4 operation frequency value conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item symbol min . typ . max . unit operation frequency system clock (iclk) f 8 ? 100 mhz peripheral module clock (pclk) 8 ? 50 external bus clock (bclk) 8 ? 25 5.3.1 clock timing table 5.5 clock timing conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v iclk = 8 to 100 mhz, bclk = 8 to 25 mhz, pclk = 8 to 50 mhz t a = - 20 to +85 c (regular specifications), t a = - 40 to + 85 c (wide - range specifications) item symbol min . max . unit test conditions clock cycle time t cyc 40 125 ns figure 5.1 clock high pulse width t ch 15 ? ns clock low pulse width t cl 15 ? ns clock rising time t cr ? 5 ns clock falling time t cf ? 5 ns oscillation settling time after reset (crystal) t osc1 10 ? ms figure 5.4 oscillation settling time after leaving software standby mode (crystal) t osc2 10 ? ms figure 5.2 oscillation settling time after leaving deep software standby mode (crystal) t osc 3 10 ? ms figure 5.3 external clock output delay settling time t dext 1 ? ms figure 5.4 external clock input low pulse width t exl 30.71 ? ns figure 5.5 external clock input high pulse width t exh 30.71 ? ns external clock rising time t exr ? 5 ns externa l clock falling time t exf ? 5 ns bclk t ch t cyc t cf t cl t cr test conditions v oh = v cc 0.7, v ol = v cc 0.3, i oh = - 1.0ma, i ol = 1.0ma, c = 30pf figure 5.1 external bus clock timing
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 61 of 84 f eb 20 , 201 3 software standby mode (power-down mode) irq exception handling irqmd[1:0] = 10b ssby = 1 wait instruction oscillation settling time t osc2 irq exception handling 01 10 ssby ssier.ssii irqmd[1:0] irq iclk oscillator figure 5. 2 oscillation settling timing after software standby mode
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 62 of 84 f eb 20 , 201 3 invalid by the internal reset irq exception handling dirqneg = 1 ssby = 1 dpsby = 1 deep software standby mode (power-down mode) reset exception handling oscillation settling time t osc3 wait instruction cleared when iokeep=l operating when iokeep=h oscillator iclk irq irq interrupt set dirqnf set request set dirqneg bit set dpsby bit cleared set iokeep bit cleared set l l i/o port operating retained iokeep bit i/o port operating retained operating dpsrstf flag internal reset l h undefined figure 5. 3 oscillation settling timing after deep software standby mode
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 63 of 84 f eb 20 , 201 3 t osc1 t dext v cc extal res# iclk figure 5. 4 oscillation settling timing t exf v cc x 0.5 extal t exh t exl t exr figure 5.5 external input clock timing
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 64 of 84 f eb 20 , 201 3 5.3.2 control signal timing table 5.6 control signal timing conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3. 0 v to av cc , v ss = pllv ss = v refl = 0 v iclk = 8 to 100 mhz, bclk = 8 to 25 mhz t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item symbol min . max . unit test conditions res# pulse width (except for rom, data fla sh programming/erasure) t resw * 1 20 ? t cyc figure 5.6 1.5 ? s internal reset time ( during rom, data flash programming/erasure) t resw 2 * 2 35 ? s nmi pulse width t nmi w 200 ? ns figure 5.7 irq pulse width t irqw 200 ? ns figure 5.8 notes: 1. both the time and the number of cycles should satisfy the specifications . 2. this is to specify the fcu reset and the wdt reset. res# t resw figure 5. 6 reset input timing nmi t nmiw figure 5.7 nmi interrupt input timing note: * ssier must be set to cancel software standby mode. irq t irqw figure 5.8 irq interrupt input timing
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 65 of 84 f eb 20 , 201 3 5.3.3 bus timing table 5.7 bus timing conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v, bcl k = 8 to 25 mhz t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) output load conditions: v oh = v cc x 0.5, v ol = v cc x 0.5, i oh = - 1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min . max . unit test conditions address d elay time t ad ? 30 ns figures 5.9 to 5 .1 2 byte control delay time t bcd ? 30 ns cs# delay time t csd ? 30 ns rd# delay time t rsd ? 20 ns rd# setup time t rss 0.5 (1/bclk) - 20 ? ns read data setup time t rds 15 ? ns read data hold time t rdh 0 ? ns wr# delay time t wrd ? 20 ns wr# setup time t wrs 0.5 (1/bclk) - 20 ? ns write data delay time t wdd ? 35 ns write data hold time t wdh 0 ? ns wait# setup time t wts 15 ? ns figure 5 .1 3 wait# hold time t wth 0 ? ns
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 66 of 84 f eb 20 , 201 3 a23 to a1 cs7# to cs0# t ad bclk a23 to a0 d15 to d0 (read) byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t bcd t w1 t rss t rss t w2 t end t n1 rdon: 1 csrwait: 2 csroff: 1 cson: 0 t h figure 5. 9 external bus timing/normal read cycle ( bu s clock synchronized )
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 67 of 84 f eb 20 , 201 3 a23 to a1 cs7# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t ad t ad t bcd t w1 d15 to d0 (write) wr0#, wr1#, wr# (write) t wrd t wrd t wdh t wdd t wrs t wrs t w2 t end t n1 t h wron: 1 wdon: 1* cswwait: 2 cswoff: 1 wdoff: 1 * cson: 0 note: * be sure to specify wdon and wdoff as at least one cycle of bclk. fi gure 5. 10 external bus timing/normal write cycle ( bus clock synchronized )
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 68 of 84 f eb 20 , 201 3 a23 to a1 cs7# to cs0# t ad bclk a23 to a0 d15 to d0 (read) byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd rd# (read) t rsd t rsd t rdh t rds t ad t bcd t w1 t rss t rss t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rss t rss t rsd t rsd t rdh t rds t rss t rss t end t pw1 t pw2 t end t n1 t h t ad t ad t ad t ad rdon: 1 csrwait: 2 csroff: 1 t rsd t rsd t rdh t rds t rss t rss t ad t ad csprwait: 2 t pw1 t pw2 t end rdon: 1 csprwait: 2 rdon: 1 csprwait: 2 rdon: 1 cson: 0 figure 5. 11 external bus timing/page read cycle ( bus clock synchronized ) a23 to a1 cs7# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t csd t ad t bcd t w1 d15 to d0 (write) wr0#, wr1#, wr# (write) t wrd t wrd t wdh t wdd t wrs t wrs t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrs t wrs t wrd t wrd t wdh t wdd t wrs t wrs t dw1 t end t pw1 t pw2 t end t n1 t h t dw1 t ad t ad t ad t ad wron: 1 wdon: 1* cswwait: 2 cspwwait: 2 wdoff: 1 * cspwwait: 2 wdoff: 1 * cswoff: 1 wdoff: 1 * cson:0 note: * be sure to specify wdon and wdoff as at least one cycle of bclk. wron: 1 wdon: 1* wron: 1 wdon: 1* figure 5. 12 external bus timing/page write cycle ( bus clock synchronized )
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 69 of 84 f eb 20 , 201 3 t wts t wth t wts t wth csrwait: 3 cswwait: 3 bclk a23 to a0 cs7# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end ) t end t w3 t n1 t h external wait figure 5. 13 external bus timing /external wait control
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 70 of 84 f eb 20 , 201 3 5.3.4 timing of on - chip peripheral modules table 5.8 timing of on - chip peripheral module s (1) conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v, pclk = 8 to 50 mhz t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) output load conditions: v oh = v cc x 0.5, v ol = v cc x 0.5, i oh = - 1.0 ma, i ol = 1.0 ma, c = 30 pf item symbol min . max . unit test conditions i/o ports output data delay time t pwd ? 40 ns figure 5. 14 input data setup time t prs 25 ? ns input data hold time t prh 25 ? ns tpu timer output delay time t tocd ? 40 ns figure 5. 15 timer input setup time t tics 25 ? ns timer clock input setup time t tcks 25 ? ns figure 5.16 timer clock pulse width single - edge setting t tckwh 1.5 x (1/ p clk ) ? t cyc both - edge setting t tckwl 2.5 x (1/ pclk ) ? t cyc ppg pulse output delay time t pod ? 40 ns figure 5. 17 8- bit timer timer output delay time t tmod ? 40 ns figure 5. 18 timer reset input setup time t tmrs 25 ? ns figure 5. 19 timer clock inpu t setup time t tmcs 25 ? ns figure 5. 20 timer clock pulse width single - edge setting t tmcwh 1.5 x (1/ pclk ) ? t cyc both - edge setting t tmcwl 2.5 x (1/ pclk ) ? t cyc wdt overflow output delay time t wovd ? 40 ns figure 5. 21 sci input clock cycle asynchronous t scyc 4 x (1/ pclk ) ? t cyc figure 5. 22 clock synchronous 6 x (1/ pclk ) ? input clock pulse width t sckw 0.4 x t scyc 0.6 x t scyc t scyc input clock rise time t sckr ? 20 ns input clock fall time t sckf ? 20 ns output clock cycle asynchronous t scyc 4 x (1/ pclk ) ? t cyc clock synchronous 6 x (1/ pclk ) ? output clock pulse width t sckw 0.4 x t scyc 0.6 x t scyc t scyc output clock rise time t sckr ? 20 ns output clock fall time t sckf ? 20 ns transmit data delay time t txd ? 40 ns figur e 5. 23 receive data setup time ( clock synchronous ) t rxs 40 ? ns receive data hold time ( clock synchronous ) t rxh 40 ? ns a/d converter trigger input setup time t trgs 25 ? ns figure 5. 24
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 71 of 84 f eb 20 , 201 3 table 5.8 timing of on - chip peripheral module s (2) conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v, pclk = 8 to 50 mhz t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item symbol min . * 1 * 2 max . unit test conditions riic (sta ndard - mode) icfer.fmpe = 0 scl input cycle time t scl 8(10) x (1/ pclk ) + 1300 ? ns figure 5 .2 5 scl input high pulse width t sclh 3(5) x (1/ pclk ) + 300 ? ns scl input low pulse width t scll 5x (1/ pclk ) + 1000 ? ns scl, sda input rising time t sr ? 1000 ns scl, sda input falling time t sf ? 300 ns scl, sda input spike pulse removal time t sp 0 4 x (1/ pclk ) ns sda input bus free time t buf 5x (1/ pclk ) + 1000 ? ns start condition input hold time t stah 3(5) x (1/ pclk ) + 300 ? ns re - start condition input setup time t stas 5x (1/ pclk ) + 1000 ? ns stop condition input setup time t stos 3(5) x (1/ pclk ) + 300 ? ns data input setup time t sdas 250 ? ns data input hold time t sdah 0 ? ns scl, sda capacitive load c b ? 400 pf riic (fast - mode) icf er.fmpe = 0 scl input cycle time t scl 8(10) x (1/ pclk ) + 600 ? ns scl input high pulse width t sclh 3(5) x (1/ pclk ) + 300 ? ns scl input low pulse width t scll 5 x (1/ pclk ) + 300 ? ns scl, sda input rising time t sr 20 + 0.1c b 300 ns scl, sda inpu t falling time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 0 4 x (1/ pclk ) ns sda input bus free time t buf 5 x (1/ pclk ) + 300 ? ns start condition input hold time t stah 3(5) x (1/ pclk ) + 300 ? ns re - start condition input setup time t stas 5 x (1/ pclk ) + 300 ? ns stop condition input setup time t stos 3(5) x (1/ pclk ) + 300 ? ns data input setup time t sdas 100 ? ns data input hold time t sdah 0 ? ns scl, sda capacitive load c b ? 400 pf
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 72 of 84 f eb 20 , 201 3 table 5.8 timing of on - ch ip peripheral module s (3) conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v, t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item symbol min . *1*2 max . unit test con ditions riic (fast - mode+) icfer.fmpe = 1 scl input cycle time t scl 8(10) x (1/pclk) + 240 ? ns figure 5 .2 5 scl input high pulse width t sclh 3(5) x (1/pclk) + 120 ? ns scl input low pulse width t scll 5 x (1/pclk) + 120 ? ns scl, sda input rising t ime t sr ? 120 ns scl, sda input falling time t sf ? 120 ns scl, sda input spike pulse removal time t sp 0 4 x (1/pclk) ns sda input bus free time t buf 5 x (1/pclk) + 120 ? ns start condition input hold time t stah 3(5) x (1/pclk) + 120 ? ns re - start condition input setup time t stas 5 x (1/pclk) + 120 ? ns stop condition input setup time t stos 3(5) x (1/pclk) + 120 ? ns data input setup time t sdas 50 ? ns data input hold time t sdah 0 ? ns scl, sda capacitive load c b ? 550 pf bounda ry scan ( 176- pin lfbga ) tck clock cycle time ttckcyc 100 ? ns figure 5 .2 6 tck clock high level pulse width ttckh 45 ? ns tck clock low level pulse width ttckl 45 ? ns tck clock rising time ttckr ? 5 ns tck clock falling time ttckf ? 5 ns trst # pulse width ttrstw 20 ? tcyc figure 5 .2 7 tms setup time ttmss 20 ? ns figure 5 .2 8 tms hold time ttmsh 20 ? ns tdi setup time ttdis 20 ? ns tdi hold time ttdih 20 ? ns tdo data delay time ttdod ? 40 ns notes:1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. 2. cb indicates the total capacity of the bus line.
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 73 of 84 f eb 20 , 201 3 pclk t1 t prs t2 t prh t pwd ports 0 to e (read) (144-pin lqfp) ports 0 to h (read) (177-pin lfbga) ports 0 to e (write) (144-pin lqfp) ports 0 to h (write) (177-pin lfbga) figure 5. 14 i/o port input/output timing output compare output* pclk input capture input * notes: * tioca0 to tioca11, tiocb0 to tiocb11, tiocc0, tiocc3, tiocc6, tiocc9, tiocd0, tiocd3, tiocd6, tiocd9 t tocd t tics figure 5. 15 tpu input/output timing pclk tclka to tclkh t tcks t tcks t tckwl t tckwh figure 5. 16 tpu clock input timing
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 74 of 84 f eb 20 , 201 3 pclk po31 to po0 t pod figure 5. 17 ppg output timing pclk tmo0 to tmo3 t tmod figure 5. 18 8- bit timer output timing pclk tmri0 to tmri3 t tmrs figure 5. 19 8- bit timer reset input timing pclk tmci0 to tmci3 t tmcs t tmcs t tmcwl t tmcwh figure 5. 20 8- bit timer clock input timing
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 75 of 84 f eb 20 , 201 3 pclk wdtovf# t wovd t wovd figure 5. 21 wdt output timing sck0 to sck6 t sckw t sckr t sckf t scyc figure 5. 22 sck clock input timing t txd t rxs t rxh sck0 to sck6 txd0 to txd6 (transmit data) rxd0 to rxd6 (receive data) figure 5. 23 sci input/output timing: clock synchronous mode pclk adtrg0# to adtrg3# t trgs figure 5. 24 a/d converter external trigger input timing
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 76 of 84 f eb 20 , 201 3 sda0, sda1 scl0, scl1 v ih v il t stah t sclh t scll p * s * t sf t sr t scl t sdah t sdas t stas t sp t stos p * t buf test conditions v ih = v cc 0.7, v il = v cc 0.3 v ol = 0.6v, i ol = 6ma (icfer.fmpe = 0) v ol = 0.4v, i ol = 15ma (icfer.fmpe = 1) sr* note: s, p, and sr represent the following conditions: s: start condition p: stop condition sr: retransmit start condition figure 5. 25 i 2 c bus interface input/output timing tck t tckcyc t tckh t tckf t tckl t tckr figure 5. 26 boundary scan tck timing res# trst# tck t trstw figure 5. 27 boundary scan t rst # timing
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 77 of 84 f eb 20 , 201 3 t tmss tck tms tdi tdo t tmsh t tdis t tdih t tdod figure 5. 28 boundary scan input/output timin g
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 78 of 84 f eb 20 , 201 3 5.4 a/d conversion characteristics table 5.9 a/d conversion characteristics conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v, pclk = 8 to 50 mhz, adclk = 4 to 50 mhz t a = - 20 to + 85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item min . typ. max . unit test conditions resolution 10 10 10 bit conversion time * 1 (ad clk = 50- mhz operation) with 0.1 - f external capacitor when the capacitor is charged enou gh * 2 0.8 (0.3) * 3 ? ? s sampling 15 states without external capacitor permissible signal source impedance (max.) = 1.0 k ? 1.0 (0.5) * 3 ? ? sampling 25 states permissible signal source impedance (max.) = 5.0 k ? 2.6 (2.1) * 3 ? ? sampling 105 states ana log input capacitance ? ? 6.0 pf inl integral nonlinearity error ( inl ) ? 1.5 3.0 lsb offset error ? 1.5 3.0 lsb full - scale error ? 1.5 3.0 lsb quantization error ? 0 .5 ? lsb absolute accuracy ? 1.5 3.0 lsb dnl differential nonlinearity error ( dnl ) ? 0 .5 1 .0 lsb notes: 1. the conversion time includes the sampling time and the comparison time. as the test conditions , the number of sampling states is indicated. 2. the scanning is not supported . 3. the value in parentheses indicates t he sampling time. 5.5 d/a conversion characteristics table 5. 10 d/a conversion characteristics conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v, pclk = 8 to 50 mhz t a = - 20 to +85 c ( regular specifications), t a = - 40 to +85 c (wide - range specifications) item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time ? ? 3 s 20- pf capacitive load absolute accuracy ? 2.0 4.0 lsb 2- m resistive load ? ? 3.0 lsb 4- m resistive load ? ? 2.0 lsb 10- m resistive load ro output resistance ? 3.6 ? k
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 79 of 84 f eb 20 , 201 3 5.6 rom (flash memory for code storage) characteristics table 5. 11 rom (flash memory for code storage) characteristics conditions : v cc = pll v cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v operating temperature range during programming/erasing : t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range specifications) item symbol min. typ. max. unit test conditions programming time 256 bytes t p256 ? 2 12 ms pclk = 50 mhz n pec 100 8 kbytes t p8k ? 45 100 ms 256 bytes t p256 ? 2.4 14.4 ms pclk = 50 mhz n pec > 100 8 kbytes t p8k ? 54 120 ms erasure time 8 kbytes t e8k ? 50 120 ms pclk = 50 mhz n pec 100 64 kbytes t e64k ? 400 875 ms 128 kbytes t e128k ? 800 1750 ms 8 kbytes t e8k ? 60 144 ms pclk = 50 mhz n pec > 100 64 kbytes t e64k ? 480 1050 ms 128 kbytes t e12 8k ? 960 2100 ms rewrite/erase cycle * 1 n pec 1000* 2 ? ? times suspend delay time during writing t spd ? ? 120 s figure 5 .29 pclk = 50 mhz first suspend delay time during erasing (in suspend p riority mode ) t sesd1 ? ? 120 s second suspend delay time during erasing (in suspend p riority mode ) t sesd2 ? ? 1.7 ms suspend delay ti me during erasing (in erasure p riority mode ) t seed ? ? 1.7 ms data hold time * 3 t drp 10 ? ? year notes: 1. definition of rewrite/erase cycle: the rewrite/erase cycle is the number of erasing for each block. when the rewrite/erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 256 - byte writing is performed 32 times for different addresses in 8- kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. however, writing to th e same address for several times as one erasing is not enabled (over writing is prohibited). 2. this indicates the minimum number that guarantees the characteristics after rewriting. (the guaranteed value is in the range from one to the minimum number.) 3. this indicates the characteristic when rewrite is performed within the specification range including the minimum number.
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 80 of 84 f eb 20 , 201 3 5.7 data flash (flash memory for data storage) characteristics table 5. 12 data flash (flash memory for data storage) characteristics conditions : v cc = pllv cc = av cc = 3.0 to 3.6 v, v refh = 3.0 v to av cc , v ss = pllv ss = v refl = 0 v operating temperature range during programming/erasing : t a = - 20 to +85 c (regular specifications), t a = - 40 to +85 c (wide - range sp ecifications) item symbol min. typ. max. unit test conditions programming time 8 bytes t dp8 ? 0.4 2 ms pclk = 50 - mhz operation 128 bytes t dp128 ? 1 5 ms erasure time 8 kbytes t d e8k ? 300 900 ms pclk = 50 - mhz operation blank check time 8 bytes t dbc8 ? ? 30 s pclk = 50 - mhz operation 8 kbytes t dbc8k ? ? 2.5 ms rewrite/erase cycle * 1 n dpec 30000* 2 ? ? times suspend delay time during writing t dspd ? ? 120 s figure 5 .29 pclk = 50 - mhz operation first suspend delay time during erasing (in suspend p rio rity mode ) t dsesd1 ? ? 120 s second suspend delay time during erasing (in suspend p riority mode ) t dsesd2 ? ? 1.7 ms suspend delay time during erasing (in erasure p riority mode ) t dseed ? ? 1.7 ms data hold time * 3 t ddrp 10 ? ? year notes: 1. definition of rewrite/erase cycle: the rewrite/erase cycle is the number of erasing for each block. when the rewrite/erase cycle is n times (n = 30000), erasing can be performed n times for each block. for instance, when 128 - byte writing is performed 64 times for different addresses in 8- kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. however, writing to the same address for several times as one erasing is not enabled (over writing is prohibited). 2. this indicates the minimum number that guarantees the characteristics after rewriting. (the guaranteed value is in the range from one to the minimum number.) 3. this indicates the characteristic when rewrite is performed within the specification range including the minimum number.
rx610 group 5 . electrical characteristics r 01ds0097ej012 0 rev.1. 20 page 81 of 84 f eb 20 , 201 3 fcu command fstatr0.frdy write pulse write suspend fcu command fstatr0.frdy erasure pulse erasure suspend in suspend priority mode fcu command fstatr0.frdy erasure pulse erasure suspend in erasure priority mode program suspend ready not ready ready programming erase suspend ready not ready ready erasing erase suspend resume suspend ready not ready ready not ready erasing erasing t spd , t dspd t sesd1 , t dsesd1 t sesd2 , t dsesd2 t seed , t dseed figure 5. 29 r om, data flash write/erase suspend timing
rx610 group appendix 1 . package dimensions r01uh0032ej01 2 0 rev.1. 20 page 82 of 84 f eb 20 , 201 3 appendix 1. package dimension s information on the latest version of the package dimension s or mountings has been displayed in " packages " on renesas technology corp. website . 176- pin lfbga (plbg0176ga - a)
rx610 group appendix 1 . package dimensions r01uh0032ej01 2 0 rev.1. 20 page 83 of 84 f eb 20 , 201 3 terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.270.220.17 max nommin dimension in millimeters symbol reference 20.120.019.9 d 20.120.019.9 e 1.4 a 2 22.222.021.8 22.222.021.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 * 1 * 2 * 3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. e 144- pin lqfp (plqp0144ka - a)
rx610 group revision history r01ds0097ej01 20 rev.1. 20 page 84 of 84 feb 20 , 20 13 revision history rx 610 group datasheet rev. data description page summary 0.50 mar. 24, 2009 ? first edition issued 1.00 apr . 22, 2011 6 7 10 to 15 21 , 25 1. overview figure 1.2 block diagram: ports f to h added figure 1.3 pin assignment of the 176 - pin lfbga , added table 1.3 list of pins and pin functions ( 176- pin lfbga ), added table 1.5 pin functions: description on the bscanp, pf0 to pf6, pg0 to pg7, and ph0 to ph7 pins added 34 to 54 4 . i/o registers table 4 .1 list of i/o registers (addre ss order), changed 58 59 60 61 71 75 75 76 5 . electrical characteristics table 5 .3 permissible output currents, changed table 5 .5 clock timing: oscillation settling time after leaving deep software standby mode (crystal), t osc 3, added figure 5 . 2 osci llation settling timing after software standby mode, changed figure 5 . 3 oscillation settling timing after deep software standby mode, added table 5 .8 timing of on - chip peripheral modules (3), changed figure 5 . 26 boundary scan tck timing, added figure 5. 27 boundary scan trst # timing , added figure 5 . 28 boundary scan input/output timing, added 1.20 feb . 20 , 201 3 5 23, 26 1. overview table 1.2 list of products, product lineup added table 1.5 pin functions, description on bus control changed, note added 35 to 55 5 . i/o register table 5.1 list of i/o registers (address order), changed all trademarks and registered trademarks are the property of their respective owners.
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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"standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . r e n esas el ec tr o ni cs am e ri ca in c . 2880 scott boulevard santa clara , ca 95050-2554 , u.s.a . tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics mala y sia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petalin g jaya, selan g or darul ehsan, malaysi a tel: +60-3-7955-9390 , fax: +60-3-7955-951 0 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2013 renesas electronics corporation. all ri g hts reserved . colo p hon 2.2

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